commit ed19583c945c128a2faf47eb53b297386f468a46 Author: IanW Date: Wed Jun 12 14:38:18 2019 +0100 Basic working SPI code. diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..b2cc9b3 --- /dev/null +++ b/Makefile @@ -0,0 +1,188 @@ +# **************************************************************************** # +# # +# Copyright (c) 2017 Andrea Loi # +# # +# Permission is hereby granted, free of charge, to any person obtaining a # +# copy of this software and associated documentation files (the "Software"), # +# to deal in the Software without restriction, including without limitation # +# the rights to use, copy, modify, merge, publish, distribute, sublicense, # +# and/or sell copies of the Software, and to permit persons to whom the # +# Software is furnished to do so, subject to the following conditions: # +# # +# The above copyright notice and this permission notice shall be included # +# in all copies or substantial portions of the Software. # +# # +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL # +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER # +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING # +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER # +# DEALINGS IN THE SOFTWARE. # +# # +# **************************************************************************** # + + + +# **************************************************************************** # +# < Project configuration variables > # +# **************************************************************************** # +# You probably need to change these. # +# **************************************************************************** # + + + +# **************************************************************************** # +# TARGET: This sets the name of the program. # +# It's used as a prefix for the output files. # +# **************************************************************************** # +TARGET = downconvert + + + +# **************************************************************************** # +# OTHER_SRCS: List here all the .c files that needs to be compiled. # +# You can separete them using a space. # +# **************************************************************************** # +OTHER_SRCS = main.c + + + +# **************************************************************************** # +# OPTFLAGS: Select GCC optimization level. # +# This is only used for the release build ("make"). # +# The debug build ("make debug") optimization flags are set # +# in DBG_OPTFLAGS down below. # +# Also be aware that some levels (usually -O3) may require you to # +# add additional support functions like memcpy and memset. # +# **************************************************************************** # +OPTFLAGS = -O0 + + + +# **************************************************************************** # +# < Advanced configuration variables > # +# **************************************************************************** # +# You probably don't need to change these. # +# **************************************************************************** # +INIT_SRC = init.c +LINKER_SCRIPT = STM32F103C8.ld +STUTIL_PORT = 4242 +DBG_OPTFLAGS = -O0 +REMOVE_OBJS = Y +VERBOSE = N +CROSS_COMPILE = arm-none-eabi- +STFLASH = st-flash +STUTIL = st-util +OPENOCD = openocd + + + +# **************************************************************************** # +# < Makefile guts > # +# **************************************************************************** # +# DON'T CHANGE ANYTHING UNLESS YOU KNOW WHAT YOU'RE DOING # +# **************************************************************************** # + +SRCS += $(INIT_SRC) +SRCS += $(OTHER_SRCS) + +OBJS = $(addsuffix .o, $(basename $(SRCS))) +SUS = $(addsuffix .su, $(basename $(OBJS))) + +CFLAGS += -mcpu=cortex-m3 -mthumb -mabi=aapcs +CFLAGS += -Wall -Wextra +CFLAGS += -fno-common -static +CFLAGS += -ffunction-sections -fdata-sections -Wl,--gc-sections + +LDFLAGS += -march=armv7-m -mabi=aapcs +LDFLAGS += -nostartfiles -nostdlib -lgcc +LDFLAGS += -T$(LINKER_SCRIPT) + +CC = $(CROSS_COMPILE)gcc +LD = $(CROSS_COMPILE)ld +OBJDUMP = $(CROSS_COMPILE)objdump +OBJCOPY = $(CROSS_COMPILE)objcopy +SIZE = $(CROSS_COMPILE)size +GDB = $(CROSS_COMPILE)gdb + +ECHO = echo +RM = rm + +ifeq ($(VERBOSE),Y) +SILENCE = +else +SILENCE = @ +endif + +GDB_PARAM = -quiet --eval-command="target extended-remote localhost:$(STUTIL_PORT)" + +.PHONY: all debug build debug_build output info size flash erase server gdb clean_objs clean + +all: clean $(SRCS) build clean_objs output size + +debug: clean $(SRCS) debug_build info output size + +build: COMFLAGS = $(OPTFLAGS) +build: $(TARGET).elf + +debug_build: COMFLAGS = $(DBG_OPTFLAGS) -ggdb3 +debug_build: CFLAGS += -fstack-usage +debug_build: LDFLAGS += -Xlinker -Map=$(TARGET).map +debug_build: $(TARGET).elf + +$(TARGET).elf: $(OBJS) + $(SILENCE)$(CC) $(LDFLAGS) $(COMFLAGS) $(OBJS) -o "$@" + +.SECONDARY: $(OBJS) + +%.o: %.c + $(SILENCE)$(CC) $(CFLAGS) $(COMFLAGS) -c "$<" -o "$@" + +output: $(TARGET).hex $(TARGET).bin + +$(TARGET).hex: $(TARGET).elf + $(SILENCE)$(OBJCOPY) -O ihex $< $@ + +$(TARGET).bin: $(TARGET).elf + $(SILENCE)$(OBJCOPY) -O binary $< $@ + +info: $(TARGET).elf + $(SILENCE)$(OBJDUMP) -x -S $(TARGET).elf > $(TARGET).lst + $(SILENCE)$(OBJDUMP) -D $(TARGET).elf > $(TARGET).dis + $(SILENCE)$(SIZE) $(TARGET).elf > $(TARGET).size + +size: $(TARGET).elf + $(SILENCE)$(SIZE) $(TARGET).elf + +flash: $(TARGET).bin + $(OPENOCD) -f /home/ianw/STM/opendps/openocd/scripts/interface/stlink-v2.cfg -f /home/ianw/STM/opendps/openocd/scripts/target/stm32f1x.cfg -c "program $(TARGET).bin verify reset exit 0x8000000" + +erase: + $(OPENOCD) -f /home/ianw/STM/opendps/openocd/scripts/interface/stlink-v2.cfg -f /home/ianw/STM/opendps/openocd/scripts/target/stm32f1x.cfg -c "flash erase_address unlock 0x08000000 0x10000" + +server: $(TARGET).elf + $(SILENCE)$(ECHO) "On another terminal run \"make gdb\"" + $(SILENCE)$(STUTIL) -p $(STUTIL_PORT) + +gdb: $(TARGET).elf + $(SILENCE)$(ECHO) "Run \"load\" to start debugging." + $(SILENCE)$(GDB) $(GDB_PARAM) $(TARGET).elf + +clean_objs: +ifeq ($(REMOVE_OBJS),Y) + $(SILENCE)$(RM) -f $(OBJS) +endif + +clean: + $(SILENCE)$(RM) -f $(TARGET).elf + $(SILENCE)$(RM) -f $(TARGET).bin + $(SILENCE)$(RM) -f $(TARGET).hex + $(SILENCE)$(RM) -f $(TARGET).size + $(SILENCE)$(RM) -f $(TARGET).lst + $(SILENCE)$(RM) -f $(TARGET).dis + $(SILENCE)$(RM) -f $(TARGET).map + $(SILENCE)$(RM) -f $(OBJS) + $(SILENCE)$(RM) -f $(SUS) + + diff --git a/STM32F103C8.ld b/STM32F103C8.ld new file mode 100644 index 0000000..c317857 --- /dev/null +++ b/STM32F103C8.ld @@ -0,0 +1,112 @@ +/* +******************************************************************************** +* * +* Copyright (c) 2017 Andrea Loi * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included * +* in all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +******************************************************************************** +*/ + + + +/******************************************************************************/ +/* DON'T EDIT THIS FILE UNLESS YOU KNOW WHAT YOU'RE DOING! */ +/******************************************************************************/ + + + +_heap_size = 0x00000400; +_stack_size = 0x00000400; + +_isrvectors_tend = 0x00000150; + +ENTRY(ResetHandler) + +MEMORY { + FLASH (RX) : ORIGIN = 0x08000000, LENGTH = 0x10000 + RAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x05000 +} + +SECTIONS { + .isrvectors 0x08000000 : + { + _sisrvectors = .; + KEEP(*(.isrvectors)) + ASSERT(. == _isrvectors_tend, "The vector table needs to be 84 elements long!"); + _eisrvectors = .; + } >FLASH + + .text : + { + . = ALIGN(4); + _stext = .; + *(.text*) + *(.rodata*) + . = ALIGN(4); + _etext = .; + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + .ARM : { + *(.ARM.exidx*) + } >FLASH + + .data : + { + . = ALIGN(4); + _sdata = .; + *(.data*) + . = ALIGN(4); + _edata = .; + } >RAM AT >FLASH + + _ldata = LOADADDR(.data); + + .bss : + { + . = ALIGN(4); + _sbss = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + } >RAM + + ._heap_trick : + { + . = ALIGN(4); + . = . + _heap_size; + . = ALIGN(4); + } >RAM + + ._stack_trick : + { + . = ALIGN(8); + . = . + _stack_size; + . = ALIGN(8); + } >RAM + +} + + diff --git a/common.h b/common.h new file mode 100644 index 0000000..cdb5638 --- /dev/null +++ b/common.h @@ -0,0 +1,132 @@ +/* +******************************************************************************** +* * +* Copyright (c) 2017 Andrea Loi * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included * +* in all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +******************************************************************************** +* This file contains common code meant to be included in every source file. * +******************************************************************************** +*/ + +#ifndef COMMON_H +#define COMMON_H + + + +// ***************************************************************************** +// * < Sized integer types > * +// ***************************************************************************** +// * If you're including stdint.h you must remove the lines below. * +// ***************************************************************************** +#define int32_t int +#define int16_t short +#define int8_t char +#define uint32_t unsigned int +#define uint16_t unsigned short +#define uint8_t unsigned char + + + +// ***************************************************************************** +// * < Bitwise operations > * +// ***************************************************************************** +// * BIT_SET(FOO, BIT_4 | BIT_2) -> set bit 4 and 2 of register FOO * +// * BIT_CLR(FOO, BIT_4 | BIT_2) -> clear bit 4 and 2 of register FOO * +// * BIT_CLR_SET(FOO, BIT_1 | BIT_5, BIT_2 | BIT_7) * +// * -> clear bit 1 and 5 and set bit 2 and 7 of register FOO * +// ***************************************************************************** +#define BIT_SET(REG, BITSET) ( (REG) |= (BITSET) ) +#define BIT_CLR(REG, BITCLR) ( (REG) &= (~(BITCLR)) ) +#define BIT_CLR_SET(REG, BITCLR, BITSET) ( (REG) = ( ( (REG) & (~(BITCLR)) ) | (BITSET) ) ) + + + +#define BIT_0 0x00000001 +#define BIT_1 0x00000002 +#define BIT_2 0x00000004 +#define BIT_3 0x00000008 +#define BIT_4 0x00000010 +#define BIT_5 0x00000020 +#define BIT_6 0x00000040 +#define BIT_7 0x00000080 +#define BIT_8 0x00000100 +#define BIT_9 0x00000200 +#define BIT_10 0x00000400 +#define BIT_11 0x00000800 +#define BIT_12 0x00001000 +#define BIT_13 0x00002000 +#define BIT_14 0x00004000 +#define BIT_15 0x00008000 +#define BIT_16 0x00010000 +#define BIT_17 0x00020000 +#define BIT_18 0x00040000 +#define BIT_19 0x00080000 +#define BIT_20 0x00100000 +#define BIT_21 0x00200000 +#define BIT_22 0x00400000 +#define BIT_23 0x00800000 +#define BIT_24 0x01000000 +#define BIT_25 0x02000000 +#define BIT_26 0x04000000 +#define BIT_27 0x08000000 +#define BIT_28 0x10000000 +#define BIT_29 0x20000000 +#define BIT_30 0x40000000 +#define BIT_31 0x80000000 + +#define MASK_0 0xFFFFFFFE +#define MASK_1 0xFFFFFFFD +#define MASK_2 0xFFFFFFFB +#define MASK_3 0xFFFFFFF7 +#define MASK_4 0xFFFFFFEF +#define MASK_5 0xFFFFFFDF +#define MASK_6 0xFFFFFFBF +#define MASK_7 0xFFFFFF7F +#define MASK_8 0xFFFFFEFF +#define MASK_9 0xFFFFFDFF +#define MASK_10 0xFFFFFBFF +#define MASK_11 0xFFFFF7FF +#define MASK_12 0xFFFFEFFF +#define MASK_13 0xFFFFDFFF +#define MASK_14 0xFFFFBFFF +#define MASK_15 0xFFFF7FFF +#define MASK_16 0xFFFEFFFF +#define MASK_17 0xFFFDFFFF +#define MASK_18 0xFFFBFFFF +#define MASK_19 0xFFF7FFFF +#define MASK_20 0xFFEFFFFF +#define MASK_21 0xFFDFFFFF +#define MASK_22 0xFFBFFFFF +#define MASK_23 0xFF7FFFFF +#define MASK_24 0xFEFFFFFF +#define MASK_25 0xFDFFFFFF +#define MASK_26 0xFBFFFFFF +#define MASK_27 0xF7FFFFFF +#define MASK_28 0xEFFFFFFF +#define MASK_29 0xDFFFFFFF +#define MASK_30 0xBFFFFFFF +#define MASK_31 0x7FFFFFFF + + + +#endif + + diff --git a/init.c b/init.c new file mode 100644 index 0000000..362a5e5 --- /dev/null +++ b/init.c @@ -0,0 +1,207 @@ +/* +******************************************************************************** +* * +* Copyright (c) 2017 Andrea Loi * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included * +* in all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +******************************************************************************** +* This file contains the interrupt vector table and the reset handler code. * +******************************************************************************** +*/ + +#include "common.h" +#include "regs.h" + + + +void ResetHandler(void); // This is the first function to be executed. +void Halt(void); // This function just runs an infinite loop. +extern int main(void); // ResetHandler will call main after initialization. + + + +// ***************************************************************************** +// * Define what to do if the cpu receives an interrupt for a peripheral that * +// * doesn't exist. This doesn't make sense and it should never happen. * +// ***************************************************************************** +#define ISR_NOT_IMPL ((uint32_t *) Halt) + + + +// ***************************************************************************** +// * Define the default interrupt function. * +// ***************************************************************************** +#define ISR_NOT_SET ((uint32_t *) Halt) + + + +// ***************************************************************************** +// * Define where the stack starts. * +// * ARM Cortex-M CPUs use a Full Descending stack, meaning the stack starts * +// * at the end of the RAM and grows towards the beginning of the RAM. * +// * An STM32F103C8 has 20KB of RAM, from 0x20000000 to 0x20004FFF. * +// * The stack bottom is set to 0x20005000 because the SP register is * +// * decremented BEFORE storing a value, therefore the first byte pushed to * +// * the stack will be at address 0x20004FFF. * +// ***************************************************************************** +#define STACK_START_ADDR 0x20005000 + + + +// ***************************************************************************** +// * Set the vector table and store it in the .isrvectors section. * +// ***************************************************************************** +uint32_t (* const vectortable[]) __attribute__ ((section(".isrvectors"))) = { + /* Function Pointer Name Addr IRQn EXn */ + (uint32_t *) STACK_START_ADDR, /* SP 0x0000 N/A N/A */ + (uint32_t *) ResetHandler, /* Reset 0x0004 N/A 1 */ + ISR_NOT_SET, /* NMI 0x0008 -14 2 */ + ISR_NOT_SET, /* HardFault 0x000C -13 3 */ + ISR_NOT_SET, /* MemManage 0x0010 -12 4 */ + ISR_NOT_SET, /* BusFault 0x0014 -11 5 */ + ISR_NOT_SET, /* UsageFault 0x0018 -10 6 */ + ISR_NOT_IMPL, /* Reserved 0x001C -9 7 */ + ISR_NOT_IMPL, /* Reserved 0x0020 -8 8 */ + ISR_NOT_IMPL, /* Reserved 0x0024 -7 9 */ + ISR_NOT_IMPL, /* Reserved 0x0028 -6 10 */ + ISR_NOT_SET, /* SVCall 0x002C -5 11 */ + ISR_NOT_SET, /* DebugMonitor 0x0030 -4 12 */ + ISR_NOT_IMPL, /* Reserved 0x0034 -3 13 */ + ISR_NOT_SET, /* PendSV 0x0038 -2 14 */ + ISR_NOT_SET, /* SysTick 0x003C -1 15 */ + ISR_NOT_SET, /* WWDG 0x0040 0 16 */ + ISR_NOT_SET, /* PVD 0x0044 1 17 */ + ISR_NOT_SET, /* TAMPER 0x0048 2 18 */ + ISR_NOT_SET, /* RTC 0x004C 3 19 */ + ISR_NOT_SET, /* FLASH 0x0050 4 20 */ + ISR_NOT_SET, /* RCC 0x0054 5 21 */ + ISR_NOT_SET, /* EXTI0 0x0058 6 22 */ + ISR_NOT_SET, /* EXTI1 0x005C 7 23 */ + ISR_NOT_SET, /* EXTI2 0x0060 8 24 */ + ISR_NOT_SET, /* EXTI3 0x0064 9 25 */ + ISR_NOT_SET, /* EXTI4 0x0068 10 26 */ + ISR_NOT_SET, /* DMA1_Channel1 0x006C 11 27 */ + ISR_NOT_SET, /* DMA1_Channel2 0x0070 12 28 */ + ISR_NOT_SET, /* DMA1_Channel3 0x0074 13 29 */ + ISR_NOT_SET, /* DMA1_Channel4 0x0078 14 30 */ + ISR_NOT_SET, /* DMA1_Channel5 0x007C 15 31 */ + ISR_NOT_SET, /* DMA1_Channel6 0x0080 16 32 */ + ISR_NOT_SET, /* DMA1_Channel7 0x0084 17 33 */ + ISR_NOT_SET, /* ADC1_2 0x0088 18 34 */ + ISR_NOT_SET, /* USB_HP_CAN_TX 0x008C 19 35 */ + ISR_NOT_SET, /* USB_LP_CAN_RX0 0x0090 20 36 */ + ISR_NOT_SET, /* CAN_RX1 0x0094 21 37 */ + ISR_NOT_SET, /* CAN_SCE 0x0098 22 38 */ + ISR_NOT_SET, /* EXTI9_5 0x009C 23 39 */ + ISR_NOT_SET, /* TIM1_BRK 0x00A0 24 40 */ + ISR_NOT_SET, /* TIM1_UP 0x00A4 25 41 */ + ISR_NOT_SET, /* TIM1_TRG_COM 0x00A8 26 42 */ + ISR_NOT_SET, /* TIM1_CC 0x00AC 27 43 */ + ISR_NOT_SET, /* TIM2 0x00B0 28 44 */ + ISR_NOT_SET, /* TIM3 0x00B4 29 45 */ + ISR_NOT_SET, /* TIM4 0x00B8 30 46 */ + ISR_NOT_SET, /* I2C1_EV 0x00BC 31 47 */ + ISR_NOT_SET, /* I2C1_ER 0x00C0 32 48 */ + ISR_NOT_SET, /* I2C2_EV 0x00C4 33 49 */ + ISR_NOT_SET, /* I2C2_ER 0x00C8 34 50 */ + ISR_NOT_SET, /* SPI1 0x00CC 35 51 */ + ISR_NOT_SET, /* SPI2 0x00D0 36 52 */ + ISR_NOT_SET, /* USART1 0x00D4 37 53 */ + ISR_NOT_SET, /* USART2 0x00D8 38 54 */ + ISR_NOT_SET, /* USART3 0x00DC 39 55 */ + ISR_NOT_SET, /* EXTI15_10 0x00E0 40 56 */ + ISR_NOT_SET, /* RTCAlarm 0x00E4 41 57 */ + ISR_NOT_SET, /* USBWakeup 0x00E8 42 58 */ + ISR_NOT_IMPL, /* TIM8_BRK 0x00EC 43 59 */ + ISR_NOT_IMPL, /* TIM8_UP 0x00F0 44 60 */ + ISR_NOT_IMPL, /* TIM8_TRG_COM 0x00F4 45 61 */ + ISR_NOT_IMPL, /* TIM8_CC 0x00F8 46 62 */ + ISR_NOT_IMPL, /* ADC3 0x00FC 47 63 */ + ISR_NOT_IMPL, /* FSMC 0x0100 48 64 */ + ISR_NOT_IMPL, /* SDIO 0x0104 49 65 */ + ISR_NOT_IMPL, /* TIM5 0x0108 50 66 */ + ISR_NOT_IMPL, /* SPI3 0x010C 51 67 */ + ISR_NOT_IMPL, /* UART4 0x0110 52 68 */ + ISR_NOT_IMPL, /* UART5 0x0114 53 69 */ + ISR_NOT_IMPL, /* TIM6 0x0118 54 70 */ + ISR_NOT_IMPL, /* TIM7 0x011C 55 71 */ + ISR_NOT_IMPL, /* DMA2_Channel1 0x0120 56 72 */ + ISR_NOT_IMPL, /* DMA2_Channel2 0x0124 57 73 */ + ISR_NOT_IMPL, /* DMA2_Channel3 0x0128 58 74 */ + ISR_NOT_IMPL, /* DMA2_Channel4 0x012C 59 75 */ + ISR_NOT_IMPL, /* DMA2_Channel5 0x0130 60 76 */ + ISR_NOT_IMPL, /* ETH 0x0134 61 77 */ + ISR_NOT_IMPL, /* ETH_WKUP 0x0138 62 78 */ + ISR_NOT_IMPL, /* CAN2_TX 0x013C 63 79 */ + ISR_NOT_IMPL, /* CAN2_RX0 0x0140 64 80 */ + ISR_NOT_IMPL, /* CAN2_RX1 0x0144 65 81 */ + ISR_NOT_IMPL, /* CAN2_SCE 0x0148 66 82 */ + ISR_NOT_IMPL /* OTG_FS 0x014C 67 83 */ +}; + + + +// ***************************************************************************** +// * This is the first function that is executed after a reset. * +// * 1. It selects the debug interface. * +// * 2. It sets the stack alignment. * +// * 3. It copies the initialized variables data from flash to RAM. * +// * 4. It clears the uninitialized variables. * +// * 5. It calls main. * +// * 6. It halts if main returns. * +// ***************************************************************************** +// * DON'T EDIT THIS FUNCTION UNLESS YOU KNOW WHAT YOU'RE DOING! * +// ***************************************************************************** +__attribute__ ((noreturn)) void ResetHandler(void){ + extern char _sdata; // .data section start + extern char _edata; // .data section end + extern char _sbss; // .bss section start + extern char _ebss; // .bss section end + extern char _ldata; // .data load address + + char *dst = &_sdata; + char *src = &_ldata; + + // enable 8-byte stack alignment to comply with AAPCS + BIT_SET(SCB->CCR, BIT_9); + + // copy initialized variables data + while ( dst < &_edata ) { *dst++ = *src++; } + + // clear uninitialized variables + for ( dst = &_sbss; dst < &_ebss; dst++ ) { *dst = 0; } + + // call main + main(); + + // halt + for(;;) {} +} + + + +// ***************************************************************************** +// * Halt the program. * +// ***************************************************************************** +__attribute__ ((noreturn)) void Halt(void){ + for(;;) {} +} + + diff --git a/main.c b/main.c new file mode 100644 index 0000000..d913e72 --- /dev/null +++ b/main.c @@ -0,0 +1,137 @@ +#include "common.h" +#include "regs.h" + +// PA01 - Indicator LED +// PA04 - NSS +// PA05 - SCK +// PA06 - MISO +// PA07 - MOSI +// PA08 - Test Push Switch +// PA11 - LD + +void Delay(uint32_t); +uint8_t SendReceiveSPIByte(uint32_t); +void SendSPIData (uint8_t,uint32_t); + +int main(void) +{ + + // Below are the ADF4350 settings for a 1 GHz -4dBm output + uint32_t ar0=0x00500000; + uint32_t ar1=0x08008011; + uint32_t ar2=0x00004e42; + uint32_t ar3=0x000004b3; + uint32_t ar4=0x00ac8024; + uint32_t ar5=0x00580005; + + // Turn on the port A + SPI1 clocks + *(uint32_t *)(RCC_BASE + 0x18) &= MASK_2 | MASK_12; + *(uint32_t *)(RCC_BASE + 0x18) |= BIT_2 | BIT_12; + + // SPI_CR2 setup + // 02 SSOE enabled so SS output is enabled in master mode + *(uint32_t *)(SPI1_BASE + 0x04) &= MASK_2; + *(uint32_t *)(SPI1_BASE + 0x04) |= BIT_2; + + // I/O + // PA01 needs to be in push pull mode thus 0 turns on the LED and 1 turns it off (0x2) - Bits + // PA04 (SPI NSS) needs to be in alternate push pull mode (0xa) 0b1010 + // PA05 (SPI SCK) needs to be in alternate push pull mode (0xa) + // PA06 (SPI MISO) is a floating input (0x4) + // PA07 (SPI MOSI) needs to be in alternate push pull mode (0xa) + *(uint32_t *)GPIOA_BASE &= 0x0000ff0f; + *(uint32_t *)GPIOA_BASE |= 0xa4aa0020; + // PA08 is a push switch input + // PA11 is a floating input + *(uint32_t *)(GPIOA_BASE + 0x04) &= 0xffff0ff0; + *(uint32_t *)(GPIOA_BASE + 0x04) |= 0x00004008; + // PA8 input pull up set P8ODR to 1 + // PA6 input pull up set P6ODR to 1 + *(uint32_t *)(GPIOA_BASE + 0x0c) &= MASK_8 | MASK_6; + *(uint32_t *)(GPIOA_BASE + 0x0c) |= BIT_8 | BIT_6; + + // SPI_CR1 setup + // 15 BIDIMODE 0 - bidirectional + // 14 BIDIOE 0 - output enabled + // 13 CRCEN 0 - CRC disabled + // 12 CRCNEXT 0 - No CRC phase + // 11 DFF 0 - 8 bit data frame + // 10 RXONLY 0 - Full duplex + // 09 SSM 0 - Software slave management enabled + // 08 SSI 0 + // 07 LSBFIRST 0 - MSB sent first + // 06 SPE 1 - SPI enabled + // 05/04/03 111 - fpCLK/256 + // 02 MSTR 1 - Master + // 01 CPOL 0 - Clock to zero when idle + // 00 CPHA 0 - First clock transition is the data edge + *(uint32_t *)(SPI1_BASE) &= 0xffff0000; + *(uint32_t *)(SPI1_BASE) |= BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2; + + // Flash the LED to show everything works + *(uint32_t *)(GPIOA_BASE + 0x14) = BIT_1; + Delay(500000); + *(uint32_t *)(GPIOA_BASE + 0x10) = BIT_1; + Delay(100000); + + + while (1) + { + // Send the setup data to the synth board + SendSPIData(0,ar0); + SendSPIData(1,ar1); + SendSPIData(2,ar2); + SendSPIData(3,ar3); + SendSPIData(4,ar4); + SendSPIData(5,ar5); + } + + // Go into an endless loop waiting for frequency lock to be achieved + while(1) + { + // Read GPIO port A + uint32_t portA = *(uint32_t *)(GPIOA_BASE + 0x08); + // Just bit 11 + portA &= BIT_11; + // If we have lock turn on the LED + if (portA == 0) *(uint32_t *)(GPIOA_BASE + 0x10) = BIT_1; + else *(uint32_t *)(GPIOA_BASE + 0x14) = BIT_1; + } +} + +// A general purpose delay +void Delay(uint32_t tmax) +{ + uint32_t i; + for (i=0;i < tmax ; i++) + { + asm("nop"); + } +} + +uint8_t SendReceiveSPIByte(uint32_t value) +{ + uint8_t lout = 0; + // Put the 8 bits to be sent into the SPI data register + *(uint32_t *)(SPI1_BASE + 0x0c) = value; + // Read a byte + uint8_t inbyte = *(uint32_t *)(SPI1_BASE + 0x0c); + + // Loop while the SPI BSY flag is high + while (lout == 0) + { + // Read the SPI status register + uint32_t statusSPI = *(uint32_t *)(SPI1_BASE + 0x08); + // Just bit 1 the transmit buffer empty flag - wait for this to go high then leave this function + statusSPI &= BIT_1; + if (statusSPI == BIT_1) lout = 1; + } + + return inbyte; +} + +void SendSPIData (uint8_t regNo,uint32_t outval) +{ + SendReceiveSPIByte(0xa0); +} + diff --git a/regs.h b/regs.h new file mode 100644 index 0000000..3b1ec5e --- /dev/null +++ b/regs.h @@ -0,0 +1,1079 @@ +/* +******************************************************************************** +* * +* Copyright (c) 2017 Andrea Loi * +* * +* Permission is hereby granted, free of charge, to any person obtaining a * +* copy of this software and associated documentation files (the "Software"), * +* to deal in the Software without restriction, including without limitation * +* the rights to use, copy, modify, merge, publish, distribute, sublicense, * +* and/or sell copies of the Software, and to permit persons to whom the * +* Software is furnished to do so, subject to the following conditions: * +* * +* The above copyright notice and this permission notice shall be included * +* in all copies or substantial portions of the Software. * +* * +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * +* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * +* DEALINGS IN THE SOFTWARE. * +* * +******************************************************************************** +* This file defines all the registers. * +******************************************************************************** +*/ + +#ifndef REGS_H +#define REGS_H + +#include "common.h" + + + +// ***************************************************************************** +// * DON'T EDIT THIS FILE UNLESS YOU KNOW WHAT YOU'RE DOING! * +// ***************************************************************************** + + + +// ***************************************************************************** +// * < Register structures > * +// ***************************************************************************** + +typedef struct { + volatile uint16_t F_SIZE; + volatile uint16_t RESERVED_1[3]; + volatile uint16_t U_ID_15_0; + volatile uint16_t U_ID_31_16; + volatile uint16_t U_ID_63_48; + volatile uint16_t U_ID_47_32; + volatile uint16_t U_ID_95_80; + volatile uint16_t U_ID_79_64; +} SIG_Type; + +typedef struct { + volatile uint32_t CR1; + volatile uint32_t CR2; + volatile uint32_t SMCR; + volatile uint32_t DIER; + volatile uint32_t SR; + volatile uint32_t EGR; + volatile uint32_t CCMR1; + volatile uint32_t CCMR2; + volatile uint32_t CCER; + volatile uint32_t CNT; + volatile uint32_t PSC; + volatile uint32_t ARR; + volatile uint32_t RESERVED_1; + volatile uint32_t CCR1; + volatile uint32_t CCR2; + volatile uint32_t CCR3; + volatile uint32_t CCR4; + volatile uint32_t RESERVED_2; + volatile uint32_t DCR; + volatile uint32_t DMAR; +} TIM2_Type; + +typedef struct { + volatile uint32_t CRH; + volatile uint32_t CRL; + volatile uint32_t PRLH; + volatile uint32_t PRLL; + volatile uint32_t DIVH; + volatile uint32_t DIVL; + volatile uint32_t CNTH; + volatile uint32_t CNTL; + volatile uint32_t ALRH; + volatile uint32_t ALRL; +} RTC_Type; + +typedef struct { + volatile uint32_t CR; + volatile uint32_t CFR; + volatile uint32_t SR; +} WWDG_Type; + +typedef struct { + volatile uint32_t KR; + volatile uint32_t PR; + volatile uint32_t RLR; + volatile uint32_t SR; +} IWDG_Type; + +typedef struct { + volatile uint32_t CR1; + volatile uint32_t CR2; + volatile uint32_t SR; + volatile uint32_t DR; + volatile uint32_t CRCPR; + volatile uint32_t RXCRCR; + volatile uint32_t TXCRCR; + volatile uint32_t I2SCFGR; + volatile uint32_t I2SPR; +} SPI1_Type; + +typedef struct { + volatile uint32_t SR; + volatile uint32_t DR; + volatile uint32_t BRR; + volatile uint32_t CR1; + volatile uint32_t CR2; + volatile uint32_t CR3; + volatile uint32_t GTPR; +} USART1_Type; + +typedef struct { + volatile uint32_t CR1; + volatile uint32_t CR2; + volatile uint32_t OAR1; + volatile uint32_t OAR2; + volatile uint32_t DR; + volatile uint32_t SR1; + volatile uint32_t SR2; + volatile uint32_t CCR; + volatile uint32_t TRISE; +} I2C1_Type; + +typedef struct { + volatile uint32_t EP0R; + volatile uint32_t EP1R; + volatile uint32_t EP2R; + volatile uint32_t EP3R; + volatile uint32_t EP4R; + volatile uint32_t EP5R; + volatile uint32_t EP6R; + volatile uint32_t EP7R; + volatile uint32_t RESERVED_1[8]; + volatile uint32_t CNTR; + volatile uint32_t ISTR; + volatile uint32_t FNR; + volatile uint32_t DADDR; + volatile uint32_t BTABLE; +} USB_Type; + +typedef struct { + volatile uint32_t CAN_MCR; + volatile uint32_t CAN_MSR; + volatile uint32_t CAN_TSR; + volatile uint32_t CAN_RF0R; + volatile uint32_t CAN_RF1R; + volatile uint32_t CAN_IER; + volatile uint32_t CAN_ESR; + volatile uint32_t CAN_BTR; + volatile uint32_t RESERVED_1[88]; + volatile uint32_t CAN_TI0R; + volatile uint32_t CAN_TDT0R; + volatile uint32_t CAN_TDL0R; + volatile uint32_t CAN_TDH0R; + volatile uint32_t CAN_TI1R; + volatile uint32_t CAN_TDT1R; + volatile uint32_t CAN_TDL1R; + volatile uint32_t CAN_TDH1R; + volatile uint32_t CAN_TI2R; + volatile uint32_t CAN_TDT2R; + volatile uint32_t CAN_TDL2R; + volatile uint32_t CAN_TDH2R; + volatile uint32_t CAN_RI0R; + volatile uint32_t CAN_RDT0R; + volatile uint32_t CAN_RDL0R; + volatile uint32_t CAN_RDH0R; + volatile uint32_t CAN_RI1R; + volatile uint32_t CAN_RDT1R; + volatile uint32_t CAN_RDL1R; + volatile uint32_t CAN_RDH1R; + volatile uint32_t RESERVED_2[12]; + volatile uint32_t CAN_FMR; + volatile uint32_t CAN_FM1R; + volatile uint32_t RESERVED_3; + volatile uint32_t CAN_FS1R; + volatile uint32_t RESERVED_4; + volatile uint32_t CAN_FFA1R; + volatile uint32_t RESERVED_5; + volatile uint32_t CAN_FA1R; + volatile uint32_t RESERVED_6[8]; + volatile uint32_t F0R1; + volatile uint32_t F0R2; + volatile uint32_t F1R1; + volatile uint32_t F1R2; + volatile uint32_t F2R1; + volatile uint32_t F2R2; + volatile uint32_t F3R1; + volatile uint32_t F3R2; + volatile uint32_t F4R1; + volatile uint32_t F4R2; + volatile uint32_t F5R1; + volatile uint32_t F5R2; + volatile uint32_t F6R1; + volatile uint32_t F6R2; + volatile uint32_t F7R1; + volatile uint32_t F7R2; + volatile uint32_t F8R1; + volatile uint32_t F8R2; + volatile uint32_t F9R1; + volatile uint32_t F9R2; + volatile uint32_t F10R1; + volatile uint32_t F10R2; + volatile uint32_t F11R1; + volatile uint32_t F11R2; + volatile uint32_t F12R1; + volatile uint32_t F12R2; + volatile uint32_t F13R1; + volatile uint32_t F13R2; +} CAN1_Type; + +typedef struct { + volatile uint32_t DR1; + volatile uint32_t DR2; + volatile uint32_t DR3; + volatile uint32_t DR4; + volatile uint32_t DR5; + volatile uint32_t DR6; + volatile uint32_t DR7; + volatile uint32_t DR8; + volatile uint32_t DR9; + volatile uint32_t DR10; + volatile uint32_t RTCCR; + volatile uint32_t CR; + volatile uint32_t CSR; + volatile uint32_t RESERVED_1[2]; + volatile uint32_t DR11; + volatile uint32_t DR12; + volatile uint32_t DR13; + volatile uint32_t DR14; + volatile uint32_t DR15; + volatile uint32_t DR16; + volatile uint32_t DR17; + volatile uint32_t DR18; + volatile uint32_t DR19; + volatile uint32_t DR20; + volatile uint32_t DR21; + volatile uint32_t DR22; + volatile uint32_t DR23; + volatile uint32_t DR24; + volatile uint32_t DR25; + volatile uint32_t DR26; + volatile uint32_t DR27; + volatile uint32_t DR28; + volatile uint32_t DR29; + volatile uint32_t DR30; + volatile uint32_t DR31; + volatile uint32_t DR32; + volatile uint32_t DR33; + volatile uint32_t DR34; + volatile uint32_t DR35; + volatile uint32_t DR36; + volatile uint32_t DR37; + volatile uint32_t DR38; + volatile uint32_t DR39; + volatile uint32_t DR40; + volatile uint32_t DR41; + volatile uint32_t DR42; +} BKP_Type; + +typedef struct { + volatile uint32_t CR; + volatile uint32_t CSR; +} PWR_Type; + +typedef struct { + volatile uint32_t EVCR; + volatile uint32_t MAPR; + volatile uint32_t EXTICR1; + volatile uint32_t EXTICR2; + volatile uint32_t EXTICR3; + volatile uint32_t EXTICR4; + volatile uint32_t RESERVED_1; + volatile uint32_t MAPR2; +} AFIO_Type; + +typedef struct { + volatile uint32_t IMR; + volatile uint32_t EMR; + volatile uint32_t RTSR; + volatile uint32_t FTSR; + volatile uint32_t SWIER; + volatile uint32_t PR; +} EXTI_Type; + +typedef struct { + volatile uint32_t CRL; + volatile uint32_t CRH; + volatile uint32_t IDR; + volatile uint32_t ODR; + volatile uint32_t BSRR; + volatile uint32_t BRR; + volatile uint32_t LCKR; +} GPIOA_Type; + +typedef struct { + volatile uint32_t SR; + volatile uint32_t CR1; + volatile uint32_t CR2; + volatile uint32_t SMPR1; + volatile uint32_t SMPR2; + volatile uint32_t JOFR1; + volatile uint32_t JOFR2; + volatile uint32_t JOFR3; + volatile uint32_t JOFR4; + volatile uint32_t HTR; + volatile uint32_t LTR; + volatile uint32_t SQR1; + volatile uint32_t SQR2; + volatile uint32_t SQR3; + volatile uint32_t JSQR; + volatile uint32_t JDR1; + volatile uint32_t JDR2; + volatile uint32_t JDR3; + volatile uint32_t JDR4; + volatile uint32_t DR; +} ADC1_Type; + +typedef struct { + volatile uint32_t SR; + volatile uint32_t CR1; + volatile uint32_t CR2; + volatile uint32_t SMPR1; + volatile uint32_t SMPR2; + volatile uint32_t JOFR1; + volatile uint32_t JOFR2; + volatile uint32_t JOFR3; + volatile uint32_t JOFR4; + volatile uint32_t HTR; + volatile uint32_t LTR; + volatile uint32_t SQR1; + volatile uint32_t SQR2; + volatile uint32_t SQR3; + volatile uint32_t JSQR; + volatile uint32_t JDR1; + volatile uint32_t JDR2; + volatile uint32_t JDR3; + volatile uint32_t JDR4; + volatile uint32_t DR; +} ADC2_Type; + +typedef struct { + volatile uint32_t CR1; + volatile uint32_t CR2; + volatile uint32_t SMCR; + volatile uint32_t DIER; + volatile uint32_t SR; + volatile uint32_t EGR; + volatile uint32_t CCMR1; + volatile uint32_t CCMR2; + volatile uint32_t CCER; + volatile uint32_t CNT; + volatile uint32_t PSC; + volatile uint32_t ARR; + volatile uint32_t RCR; + volatile uint32_t CCR1; + volatile uint32_t CCR2; + volatile uint32_t CCR3; + volatile uint32_t CCR4; + volatile uint32_t BDTR; + volatile uint32_t DCR; + volatile uint32_t DMAR; +} TIM1_Type; + +typedef struct { + volatile uint32_t ISR; + volatile uint32_t IFCR; + volatile uint32_t CCR1; + volatile uint32_t CNDTR1; + volatile uint32_t CPAR1; + volatile uint32_t CMAR1; + volatile uint32_t RESERVED_1; + volatile uint32_t CCR2; + volatile uint32_t CNDTR2; + volatile uint32_t CPAR2; + volatile uint32_t CMAR2; + volatile uint32_t RESERVED_2; + volatile uint32_t CCR3; + volatile uint32_t CNDTR3; + volatile uint32_t CPAR3; + volatile uint32_t CMAR3; + volatile uint32_t RESERVED_3; + volatile uint32_t CCR4; + volatile uint32_t CNDTR4; + volatile uint32_t CPAR4; + volatile uint32_t CMAR4; + volatile uint32_t RESERVED_4; + volatile uint32_t CCR5; + volatile uint32_t CNDTR5; + volatile uint32_t CPAR5; + volatile uint32_t CMAR5; + volatile uint32_t RESERVED_5; + volatile uint32_t CCR6; + volatile uint32_t CNDTR6; + volatile uint32_t CPAR6; + volatile uint32_t CMAR6; + volatile uint32_t RESERVED_6; + volatile uint32_t CCR7; + volatile uint32_t CNDTR7; + volatile uint32_t CPAR7; + volatile uint32_t CMAR7; +} DMA1_Type; + +typedef struct { + volatile uint32_t CR; + volatile uint32_t CFGR; + volatile uint32_t CIR; + volatile uint32_t APB2RSTR; + volatile uint32_t APB1RSTR; + volatile uint32_t AHBENR; + volatile uint32_t APB2ENR; + volatile uint32_t APB1ENR; + volatile uint32_t BDCR; + volatile uint32_t CSR; +} RCC_Type; + +typedef struct { + volatile uint32_t ACR; + volatile uint32_t KEYR; + volatile uint32_t OPTKEYR; + volatile uint32_t SR; + volatile uint32_t CR; + volatile uint32_t AR; + volatile uint32_t RESERVED_1; + volatile uint32_t OBR; + volatile uint32_t WRPR; +} FLASH_Type; + +typedef struct { + volatile uint32_t DR; + volatile uint32_t IDR; + volatile uint32_t CR; +} CRC_Type; + +typedef struct { + volatile uint32_t RESERVED_1; + volatile uint32_t ICTR; + volatile uint32_t RESERVED_2[62]; + volatile uint32_t ISER0; + volatile uint32_t ISER1; + volatile uint32_t RESERVED_3[30]; + volatile uint32_t ICER0; + volatile uint32_t ICER1; + volatile uint32_t RESERVED_4[30]; + volatile uint32_t ISPR0; + volatile uint32_t ISPR1; + volatile uint32_t RESERVED_5[30]; + volatile uint32_t ICPR0; + volatile uint32_t ICPR1; + volatile uint32_t RESERVED_6[30]; + volatile uint32_t IABR0; + volatile uint32_t IABR1; + volatile uint32_t RESERVED_7[62]; + volatile uint32_t IPR0; + volatile uint32_t IPR1; + volatile uint32_t IPR2; + volatile uint32_t IPR3; + volatile uint32_t IPR4; + volatile uint32_t IPR5; + volatile uint32_t IPR6; + volatile uint32_t IPR7; + volatile uint32_t IPR8; + volatile uint32_t IPR9; + volatile uint32_t IPR10; + volatile uint32_t IPR11; + volatile uint32_t IPR12; + volatile uint32_t IPR13; + volatile uint32_t IPR14; + volatile uint32_t RESERVED_8[689]; + volatile uint32_t STIR; +} NVIC_Type; + +typedef struct { + volatile uint32_t CTRL; + volatile uint32_t LOAD; + volatile uint32_t VAL; + volatile uint32_t CALIB; +} STK_Type; + +typedef struct { + volatile uint32_t CPUID; + volatile uint32_t ICSR; + volatile uint32_t VTOR; + volatile uint32_t AIRCR; + volatile uint32_t SCR; + volatile uint32_t CCR; + volatile uint32_t SHPR1; + volatile uint32_t SHPR2; + volatile uint32_t SHPR3; + volatile uint32_t SHCRS; + volatile uint32_t CFSR; + volatile uint32_t HFSR; + volatile uint32_t RESERVED_1; + volatile uint32_t MMAR; + volatile uint32_t BFAR; +} SCB_Type; + +typedef struct { + volatile uint32_t IDCODE; + volatile uint32_t CR; +} DBG_Type; + + + +// ***************************************************************************** +// * < Register base addresses > * +// ***************************************************************************** + +#define SIG_BASE ((uint32_t) 0x1FFFF7E0) +#define TIM2_BASE ((uint32_t) 0x40000000) +#define TIM3_BASE ((uint32_t) 0x40000400) +#define TIM4_BASE ((uint32_t) 0x40000800) +#define RTC_BASE ((uint32_t) 0x40002800) +#define WWDG_BASE ((uint32_t) 0x40002C00) +#define IWDG_BASE ((uint32_t) 0x40003000) +#define SPI2_BASE ((uint32_t) 0x40003800) +#define USART2_BASE ((uint32_t) 0x40004400) +#define USART3_BASE ((uint32_t) 0x40004800) +#define I2C1_BASE ((uint32_t) 0x40005400) +#define I2C2_BASE ((uint32_t) 0x40005800) +#define USB_BASE ((uint32_t) 0x40005C00) +#define CAN1_BASE ((uint32_t) 0x40006400) +#define BKP_BASE ((uint32_t) 0x40006C00) +#define PWR_BASE ((uint32_t) 0x40007000) +#define AFIO_BASE ((uint32_t) 0x40010000) +#define EXTI_BASE ((uint32_t) 0x40010400) +#define GPIOA_BASE ((uint32_t) 0x40010800) +#define GPIOB_BASE ((uint32_t) 0x40010C00) +#define GPIOC_BASE ((uint32_t) 0x40011000) +#define GPIOD_BASE ((uint32_t) 0x40011400) +#define ADC1_BASE ((uint32_t) 0x40012400) +#define ADC2_BASE ((uint32_t) 0x40012800) +#define TIM1_BASE ((uint32_t) 0x40012C00) +#define SPI1_BASE ((uint32_t) 0x40013000) +#define USART1_BASE ((uint32_t) 0x40013800) +#define DMA1_BASE ((uint32_t) 0x40020000) +#define RCC_BASE ((uint32_t) 0x40021000) +#define FLASH_BASE ((uint32_t) 0x40022000) +#define CRC_BASE ((uint32_t) 0x40023000) +#define NVIC_BASE ((uint32_t) 0xE000E000) +#define STK_BASE ((uint32_t) 0xE000E010) +#define SCB_BASE ((uint32_t) 0xE000ED00) +#define DBG_BASE ((uint32_t) 0xE0042000) + + + +// ***************************************************************************** +// * < Register locations assignment > * +// ***************************************************************************** + +#define SIG ( (SIG_Type*) SIG_BASE ) +#define TIM2 ( (TIM2_Type*) TIM2_BASE ) +#define TIM3 ( (TIM2_Type*) TIM3_BASE ) +#define TIM4 ( (TIM2_Type*) TIM4_BASE ) +#define RTC ( (RTC_Type*) RTC_BASE ) +#define WWDG ( (WWDG_Type*) WWDG_BASE ) +#define IWDG ( (IWDG_Type*) IWDG_BASE ) +#define SPI2 ( (SPI1_Type*) SPI2_BASE ) +#define USART2 ( (USART1_Type*) USART2_BASE ) +#define USART3 ( (USART1_Type*) USART3_BASE ) +#define I2C1 ( (I2C1_Type*) I2C1_BASE ) +#define I2C2 ( (I2C1_Type*) I2C2_BASE ) +#define USB ( (USB_Type*) USB_BASE ) +#define CAN1 ( (CAN1_Type*) CAN1_BASE ) +#define BKP ( (BKP_Type*) BKP_BASE ) +#define PWR ( (PWR_Type*) PWR_BASE ) +#define AFIO ( (AFIO_Type*) AFIO_BASE ) +#define EXTI ( (EXTI_Type*) EXTI_BASE ) +#define GPIOA ( (GPIOA_Type*) GPIOA_BASE ) +#define GPIOB ( (GPIOA_Type*) GPIOB_BASE ) +#define GPIOC ( (GPIOA_Type*) GPIOC_BASE ) +#define GPIOD ( (GPIOA_Type*) GPIOD_BASE ) +#define ADC1 ( (ADC1_Type*) ADC1_BASE ) +#define ADC2 ( (ADC2_Type*) ADC2_BASE ) +#define TIM1 ( (TIM1_Type*) TIM1_BASE ) +#define SPI1 ( (SPI1_Type*) SPI1_BASE ) +#define USART1 ( (USART1_Type*) USART1_BASE ) +#define DMA1 ( (DMA1_Type*) DMA1_BASE ) +#define RCC ( (RCC_Type*) RCC_BASE ) +#define FLASH ( (FLASH_Type*) FLASH_BASE ) +#define CRC ( (CRC_Type*) CRC_BASE ) +#define NVIC ( (NVIC_Type*) NVIC_BASE ) +#define STK ( (STK_Type*) STK_BASE ) +#define SCB ( (SCB_Type*) SCB_BASE ) +#define DBG ( (DBG_Type*) DBG_BASE ) + + + +// ***************************************************************************** +// * < Bit-banding register structures > * +// ***************************************************************************** + +typedef struct { + volatile uint32_t CR1[32]; + volatile uint32_t CR2[32]; + volatile uint32_t SMCR[32]; + volatile uint32_t DIER[32]; + volatile uint32_t SR[32]; + volatile uint32_t EGR[32]; + volatile uint32_t CCMR1[32]; + volatile uint32_t CCMR2[32]; + volatile uint32_t CCER[32]; + volatile uint32_t CNT[32]; + volatile uint32_t PSC[32]; + volatile uint32_t ARR[32]; + volatile uint32_t RESERVED_1[32]; + volatile uint32_t CCR1[32]; + volatile uint32_t CCR2[32]; + volatile uint32_t CCR3[32]; + volatile uint32_t CCR4[32]; + volatile uint32_t RESERVED_2[32]; + volatile uint32_t DCR[32]; + volatile uint32_t DMAR[32]; +} TIM2_BB_Type; + +typedef struct { + volatile uint32_t CRH[32]; + volatile uint32_t CRL[32]; + volatile uint32_t PRLH[32]; + volatile uint32_t PRLL[32]; + volatile uint32_t DIVH[32]; + volatile uint32_t DIVL[32]; + volatile uint32_t CNTH[32]; + volatile uint32_t CNTL[32]; + volatile uint32_t ALRH[32]; + volatile uint32_t ALRL[32]; +} RTC_BB_Type; + +typedef struct { + volatile uint32_t CR[32]; + volatile uint32_t CFR[32]; + volatile uint32_t SR[32]; +} WWDG_BB_Type; + +typedef struct { + volatile uint32_t KR[32]; + volatile uint32_t PR[32]; + volatile uint32_t RLR[32]; + volatile uint32_t SR[32]; +} IWDG_BB_Type; + +typedef struct { + volatile uint32_t CR1[32]; + volatile uint32_t CR2[32]; + volatile uint32_t SR[32]; + volatile uint32_t DR[32]; + volatile uint32_t CRCPR[32]; + volatile uint32_t RXCRCR[32]; + volatile uint32_t TXCRCR[32]; + volatile uint32_t I2SCFGR[32]; + volatile uint32_t I2SPR[32]; +} SPI1_BB_Type; + +typedef struct { + volatile uint32_t SR[32]; + volatile uint32_t DR[32]; + volatile uint32_t BRR[32]; + volatile uint32_t CR1[32]; + volatile uint32_t CR2[32]; + volatile uint32_t CR3[32]; + volatile uint32_t GTPR[32]; +} USART1_BB_Type; + +typedef struct { + volatile uint32_t CR1[32]; + volatile uint32_t CR2[32]; + volatile uint32_t OAR1[32]; + volatile uint32_t OAR2[32]; + volatile uint32_t DR[32]; + volatile uint32_t SR1[32]; + volatile uint32_t SR2[32]; + volatile uint32_t CCR[32]; + volatile uint32_t TRISE[32]; +} I2C1_BB_Type; + +typedef struct { + volatile uint32_t EP0R[32]; + volatile uint32_t EP1R[32]; + volatile uint32_t EP2R[32]; + volatile uint32_t EP3R[32]; + volatile uint32_t EP4R[32]; + volatile uint32_t EP5R[32]; + volatile uint32_t EP6R[32]; + volatile uint32_t EP7R[32]; + volatile uint32_t RESERVED_1[8][32]; + volatile uint32_t CNTR[32]; + volatile uint32_t ISTR[32]; + volatile uint32_t FNR[32]; + volatile uint32_t DADDR[32]; + volatile uint32_t BTABLE[32]; +} USB_BB_Type; + +typedef struct { + volatile uint32_t CAN_MCR[32]; + volatile uint32_t CAN_MSR[32]; + volatile uint32_t CAN_TSR[32]; + volatile uint32_t CAN_RF0R[32]; + volatile uint32_t CAN_RF1R[32]; + volatile uint32_t CAN_IER[32]; + volatile uint32_t CAN_ESR[32]; + volatile uint32_t CAN_BTR[32]; + volatile uint32_t RESERVED_1[88][32]; + volatile uint32_t CAN_TI0R[32]; + volatile uint32_t CAN_TDT0R[32]; + volatile uint32_t CAN_TDL0R[32]; + volatile uint32_t CAN_TDH0R[32]; + volatile uint32_t CAN_TI1R[32]; + volatile uint32_t CAN_TDT1R[32]; + volatile uint32_t CAN_TDL1R[32]; + volatile uint32_t CAN_TDH1R[32]; + volatile uint32_t CAN_TI2R[32]; + volatile uint32_t CAN_TDT2R[32]; + volatile uint32_t CAN_TDL2R[32]; + volatile uint32_t CAN_TDH2R[32]; + volatile uint32_t CAN_RI0R[32]; + volatile uint32_t CAN_RDT0R[32]; + volatile uint32_t CAN_RDL0R[32]; + volatile uint32_t CAN_RDH0R[32]; + volatile uint32_t CAN_RI1R[32]; + volatile uint32_t CAN_RDT1R[32]; + volatile uint32_t CAN_RDL1R[32]; + volatile uint32_t CAN_RDH1R[32]; + volatile uint32_t RESERVED_2[12][32]; + volatile uint32_t CAN_FMR[32]; + volatile uint32_t CAN_FM1R[32]; + volatile uint32_t RESERVED_3[32]; + volatile uint32_t CAN_FS1R[32]; + volatile uint32_t RESERVED_4[32]; + volatile uint32_t CAN_FFA1R[32]; + volatile uint32_t RESERVED_5[32]; + volatile uint32_t CAN_FA1R[32]; + volatile uint32_t RESERVED_6[8][32]; + volatile uint32_t F0R1[32]; + volatile uint32_t F0R2[32]; + volatile uint32_t F1R1[32]; + volatile uint32_t F1R2[32]; + volatile uint32_t F2R1[32]; + volatile uint32_t F2R2[32]; + volatile uint32_t F3R1[32]; + volatile uint32_t F3R2[32]; + volatile uint32_t F4R1[32]; + volatile uint32_t F4R2[32]; + volatile uint32_t F5R1[32]; + volatile uint32_t F5R2[32]; + volatile uint32_t F6R1[32]; + volatile uint32_t F6R2[32]; + volatile uint32_t F7R1[32]; + volatile uint32_t F7R2[32]; + volatile uint32_t F8R1[32]; + volatile uint32_t F8R2[32]; + volatile uint32_t F9R1[32]; + volatile uint32_t F9R2[32]; + volatile uint32_t F10R1[32]; + volatile uint32_t F10R2[32]; + volatile uint32_t F11R1[32]; + volatile uint32_t F11R2[32]; + volatile uint32_t F12R1[32]; + volatile uint32_t F12R2[32]; + volatile uint32_t F13R1[32]; + volatile uint32_t F13R2[32]; +} CAN1_BB_Type; + +typedef struct { + volatile uint32_t DR1[32]; + volatile uint32_t DR2[32]; + volatile uint32_t DR3[32]; + volatile uint32_t DR4[32]; + volatile uint32_t DR5[32]; + volatile uint32_t DR6[32]; + volatile uint32_t DR7[32]; + volatile uint32_t DR8[32]; + volatile uint32_t DR9[32]; + volatile uint32_t DR10[32]; + volatile uint32_t RTCCR[32]; + volatile uint32_t CR[32]; + volatile uint32_t CSR[32]; + volatile uint32_t RESERVED_1[2][32]; + volatile uint32_t DR11[32]; + volatile uint32_t DR12[32]; + volatile uint32_t DR13[32]; + volatile uint32_t DR14[32]; + volatile uint32_t DR15[32]; + volatile uint32_t DR16[32]; + volatile uint32_t DR17[32]; + volatile uint32_t DR18[32]; + volatile uint32_t DR19[32]; + volatile uint32_t DR20[32]; + volatile uint32_t DR21[32]; + volatile uint32_t DR22[32]; + volatile uint32_t DR23[32]; + volatile uint32_t DR24[32]; + volatile uint32_t DR25[32]; + volatile uint32_t DR26[32]; + volatile uint32_t DR27[32]; + volatile uint32_t DR28[32]; + volatile uint32_t DR29[32]; + volatile uint32_t DR30[32]; + volatile uint32_t DR31[32]; + volatile uint32_t DR32[32]; + volatile uint32_t DR33[32]; + volatile uint32_t DR34[32]; + volatile uint32_t DR35[32]; + volatile uint32_t DR36[32]; + volatile uint32_t DR37[32]; + volatile uint32_t DR38[32]; + volatile uint32_t DR39[32]; + volatile uint32_t DR40[32]; + volatile uint32_t DR41[32]; + volatile uint32_t DR42[32]; +} BKP_BB_Type; + +typedef struct { + volatile uint32_t CR[32]; + volatile uint32_t CSR[32]; +} PWR_BB_Type; + +typedef struct { + volatile uint32_t EVCR[32]; + volatile uint32_t MAPR[32]; + volatile uint32_t EXTICR1[32]; + volatile uint32_t EXTICR2[32]; + volatile uint32_t EXTICR3[32]; + volatile uint32_t EXTICR4[32]; + volatile uint32_t RESERVED_1[32]; + volatile uint32_t MAPR2[32]; +} AFIO_BB_Type; + +typedef struct { + volatile uint32_t IMR[32]; + volatile uint32_t EMR[32]; + volatile uint32_t RTSR[32]; + volatile uint32_t FTSR[32]; + volatile uint32_t SWIER[32]; + volatile uint32_t PR[32]; +} EXTI_BB_Type; + +typedef struct { + volatile uint32_t CRL[32]; + volatile uint32_t CRH[32]; + volatile uint32_t IDR[32]; + volatile uint32_t ODR[32]; + volatile uint32_t BSRR[32]; + volatile uint32_t BRR[32]; + volatile uint32_t LCKR[32]; +} GPIOA_BB_Type; + +typedef struct { + volatile uint32_t SR[32]; + volatile uint32_t CR1[32]; + volatile uint32_t CR2[32]; + volatile uint32_t SMPR1[32]; + volatile uint32_t SMPR2[32]; + volatile uint32_t JOFR1[32]; + volatile uint32_t JOFR2[32]; + volatile uint32_t JOFR3[32]; + volatile uint32_t JOFR4[32]; + volatile uint32_t HTR[32]; + volatile uint32_t LTR[32]; + volatile uint32_t SQR1[32]; + volatile uint32_t SQR2[32]; + volatile uint32_t SQR3[32]; + volatile uint32_t JSQR[32]; + volatile uint32_t JDR1[32]; + volatile uint32_t JDR2[32]; + volatile uint32_t JDR3[32]; + volatile uint32_t JDR4[32]; + volatile uint32_t DR[32]; +} ADC1_BB_Type; + +typedef struct { + volatile uint32_t SR[32]; + volatile uint32_t CR1[32]; + volatile uint32_t CR2[32]; + volatile uint32_t SMPR1[32]; + volatile uint32_t SMPR2[32]; + volatile uint32_t JOFR1[32]; + volatile uint32_t JOFR2[32]; + volatile uint32_t JOFR3[32]; + volatile uint32_t JOFR4[32]; + volatile uint32_t HTR[32]; + volatile uint32_t LTR[32]; + volatile uint32_t SQR1[32]; + volatile uint32_t SQR2[32]; + volatile uint32_t SQR3[32]; + volatile uint32_t JSQR[32]; + volatile uint32_t JDR1[32]; + volatile uint32_t JDR2[32]; + volatile uint32_t JDR3[32]; + volatile uint32_t JDR4[32]; + volatile uint32_t DR[32]; +} ADC2_BB_Type; + +typedef struct { + volatile uint32_t CR1[32]; + volatile uint32_t CR2[32]; + volatile uint32_t SMCR[32]; + volatile uint32_t DIER[32]; + volatile uint32_t SR[32]; + volatile uint32_t EGR[32]; + volatile uint32_t CCMR1[32]; + volatile uint32_t CCMR2[32]; + volatile uint32_t CCER[32]; + volatile uint32_t CNT[32]; + volatile uint32_t PSC[32]; + volatile uint32_t ARR[32]; + volatile uint32_t RCR[32]; + volatile uint32_t CCR1[32]; + volatile uint32_t CCR2[32]; + volatile uint32_t CCR3[32]; + volatile uint32_t CCR4[32]; + volatile uint32_t BDTR[32]; + volatile uint32_t DCR[32]; + volatile uint32_t DMAR[32]; +} TIM1_BB_Type; + +typedef struct { + volatile uint32_t ISR[32]; + volatile uint32_t IFCR[32]; + volatile uint32_t CCR1[32]; + volatile uint32_t CNDTR1[32]; + volatile uint32_t CPAR1[32]; + volatile uint32_t CMAR1[32]; + volatile uint32_t RESERVED_1[32]; + volatile uint32_t CCR2[32]; + volatile uint32_t CNDTR2[32]; + volatile uint32_t CPAR2[32]; + volatile uint32_t CMAR2[32]; + volatile uint32_t RESERVED_2[32]; + volatile uint32_t CCR3[32]; + volatile uint32_t CNDTR3[32]; + volatile uint32_t CPAR3[32]; + volatile uint32_t CMAR3[32]; + volatile uint32_t RESERVED_3[32]; + volatile uint32_t CCR4[32]; + volatile uint32_t CNDTR4[32]; + volatile uint32_t CPAR4[32]; + volatile uint32_t CMAR4[32]; + volatile uint32_t RESERVED_4[32]; + volatile uint32_t CCR5[32]; + volatile uint32_t CNDTR5[32]; + volatile uint32_t CPAR5[32]; + volatile uint32_t CMAR5[32]; + volatile uint32_t RESERVED_5[32]; + volatile uint32_t CCR6[32]; + volatile uint32_t CNDTR6[32]; + volatile uint32_t CPAR6[32]; + volatile uint32_t CMAR6[32]; + volatile uint32_t RESERVED_6[32]; + volatile uint32_t CCR7[32]; + volatile uint32_t CNDTR7[32]; + volatile uint32_t CPAR7[32]; + volatile uint32_t CMAR7[32]; +} DMA1_BB_Type; + +typedef struct { + volatile uint32_t CR[32]; + volatile uint32_t CFGR[32]; + volatile uint32_t CIR[32]; + volatile uint32_t APB2RSTR[32]; + volatile uint32_t APB1RSTR[32]; + volatile uint32_t AHBENR[32]; + volatile uint32_t APB2ENR[32]; + volatile uint32_t APB1ENR[32]; + volatile uint32_t BDCR[32]; + volatile uint32_t CSR[32]; +} RCC_BB_Type; + +typedef struct { + volatile uint32_t ACR[32]; + volatile uint32_t KEYR[32]; + volatile uint32_t OPTKEYR[32]; + volatile uint32_t SR[32]; + volatile uint32_t CR[32]; + volatile uint32_t AR[32]; + volatile uint32_t RESERVED_1[32]; + volatile uint32_t OBR[32]; + volatile uint32_t WRPR[32]; +} FLASH_BB_Type; + +typedef struct { + volatile uint32_t DR[32]; + volatile uint32_t IDR[32]; + volatile uint32_t CR[32]; +} CRC_BB_Type; + + + +// ***************************************************************************** +// * < Bit-banding base addresses > * +// ***************************************************************************** + +#define TIM2_BB_BASE ((uint32_t) 0x42000000) +#define TIM3_BB_BASE ((uint32_t) 0x42008000) +#define TIM4_BB_BASE ((uint32_t) 0x42010000) +#define RTC_BB_BASE ((uint32_t) 0x42050000) +#define WWDG_BB_BASE ((uint32_t) 0x42058000) +#define IWDG_BB_BASE ((uint32_t) 0x42060000) +#define SPI2_BB_BASE ((uint32_t) 0x42070000) +#define USART2_BB_BASE ((uint32_t) 0x42088000) +#define USART3_BB_BASE ((uint32_t) 0x42090000) +#define I2C1_BB_BASE ((uint32_t) 0x420A8000) +#define I2C2_BB_BASE ((uint32_t) 0x420B0000) +#define USB_BB_BASE ((uint32_t) 0x420B8000) +#define CAN1_BB_BASE ((uint32_t) 0x420C8000) +#define BKP_BB_BASE ((uint32_t) 0x420D8000) +#define PWR_BB_BASE ((uint32_t) 0x420E0000) +#define AFIO_BB_BASE ((uint32_t) 0x42200000) +#define EXTI_BB_BASE ((uint32_t) 0x42208000) +#define GPIOA_BB_BASE ((uint32_t) 0x42210000) +#define GPIOB_BB_BASE ((uint32_t) 0x42218000) +#define GPIOC_BB_BASE ((uint32_t) 0x42220000) +#define GPIOD_BB_BASE ((uint32_t) 0x42228000) +#define ADC1_BB_BASE ((uint32_t) 0x42248000) +#define ADC2_BB_BASE ((uint32_t) 0x42250000) +#define TIM1_BB_BASE ((uint32_t) 0x42258000) +#define SPI1_BB_BASE ((uint32_t) 0x42260000) +#define USART1_BB_BASE ((uint32_t) 0x42270000) +#define DMA1_BB_BASE ((uint32_t) 0x42400000) +#define RCC_BB_BASE ((uint32_t) 0x42420000) +#define FLASH_BB_BASE ((uint32_t) 0x42440000) +#define CRC_BB_BASE ((uint32_t) 0x42460000) + + + +// ***************************************************************************** +// * < Bit-banding locations assignment > * +// ***************************************************************************** + +#define BB_TIM2 ( (TIM2_BB_Type*) TIM2_BB_BASE ) +#define BB_TIM3 ( (TIM2_BB_Type*) TIM3_BB_BASE ) +#define BB_TIM4 ( (TIM2_BB_Type*) TIM4_BB_BASE ) +#define BB_RTC ( (RTC_BB_Type*) RTC_BB_BASE ) +#define BB_WWDG ( (WWDG_BB_Type*) WWDG_BB_BASE ) +#define BB_IWDG ( (IWDG_BB_Type*) IWDG_BB_BASE ) +#define BB_SPI2 ( (SPI1_BB_Type*) SPI2_BB_BASE ) +#define BB_USART2 ( (USART1_BB_Type*) USART2_BB_BASE ) +#define BB_USART3 ( (USART1_BB_Type*) USART3_BB_BASE ) +#define BB_I2C1 ( (I2C1_BB_Type*) I2C1_BB_BASE ) +#define BB_I2C2 ( (I2C1_BB_Type*) I2C2_BB_BASE ) +#define BB_USB ( (USB_BB_Type*) USB_BB_BASE ) +#define BB_CAN1 ( (CAN1_BB_Type*) CAN1_BB_BASE ) +#define BB_BKP ( (BKP_BB_Type*) BKP_BB_BASE ) +#define BB_PWR ( (PWR_BB_Type*) PWR_BB_BASE ) +#define BB_AFIO ( (AFIO_BB_Type*) AFIO_BB_BASE ) +#define BB_EXTI ( (EXTI_BB_Type*) EXTI_BB_BASE ) +#define BB_GPIOA ( (GPIOA_BB_Type*) GPIOA_BB_BASE ) +#define BB_GPIOB ( (GPIOA_BB_Type*) GPIOB_BB_BASE ) +#define BB_GPIOC ( (GPIOA_BB_Type*) GPIOC_BB_BASE ) +#define BB_GPIOD ( (GPIOA_BB_Type*) GPIOD_BB_BASE ) +#define BB_ADC1 ( (ADC1_BB_Type*) ADC1_BB_BASE ) +#define BB_ADC2 ( (ADC2_BB_Type*) ADC2_BB_BASE ) +#define BB_TIM1 ( (TIM1_BB_Type*) TIM1_BB_BASE ) +#define BB_SPI1 ( (SPI1_BB_Type*) SPI1_BB_BASE ) +#define BB_USART1 ( (USART1_BB_Type*) USART1_BB_BASE ) +#define BB_DMA1 ( (DMA1_BB_Type*) DMA1_BB_BASE ) +#define BB_RCC ( (RCC_BB_Type*) RCC_BB_BASE ) +#define BB_FLASH ( (FLASH_BB_Type*) FLASH_BB_BASE ) +#define BB_CRC ( (CRC_BB_Type*) CRC_BB_BASE ) + + + +#endif + +