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Basic working SPI code.

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IanW 2019-06-12 14:38:18 +01:00
commit ed19583c94
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188
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# **************************************************************************** #
# #
# Copyright (c) 2017 Andrea Loi #
# #
# Permission is hereby granted, free of charge, to any person obtaining a #
# copy of this software and associated documentation files (the "Software"), #
# to deal in the Software without restriction, including without limitation #
# the rights to use, copy, modify, merge, publish, distribute, sublicense, #
# and/or sell copies of the Software, and to permit persons to whom the #
# Software is furnished to do so, subject to the following conditions: #
# #
# The above copyright notice and this permission notice shall be included #
# in all copies or substantial portions of the Software. #
# #
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR #
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, #
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL #
# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER #
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING #
# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER #
# DEALINGS IN THE SOFTWARE. #
# #
# **************************************************************************** #
# **************************************************************************** #
# < Project configuration variables > #
# **************************************************************************** #
# You probably need to change these. #
# **************************************************************************** #
# **************************************************************************** #
# TARGET: This sets the name of the program. #
# It's used as a prefix for the output files. #
# **************************************************************************** #
TARGET = downconvert
# **************************************************************************** #
# OTHER_SRCS: List here all the .c files that needs to be compiled. #
# You can separete them using a space. #
# **************************************************************************** #
OTHER_SRCS = main.c
# **************************************************************************** #
# OPTFLAGS: Select GCC optimization level. #
# This is only used for the release build ("make"). #
# The debug build ("make debug") optimization flags are set #
# in DBG_OPTFLAGS down below. #
# Also be aware that some levels (usually -O3) may require you to #
# add additional support functions like memcpy and memset. #
# **************************************************************************** #
OPTFLAGS = -O0
# **************************************************************************** #
# < Advanced configuration variables > #
# **************************************************************************** #
# You probably don't need to change these. #
# **************************************************************************** #
INIT_SRC = init.c
LINKER_SCRIPT = STM32F103C8.ld
STUTIL_PORT = 4242
DBG_OPTFLAGS = -O0
REMOVE_OBJS = Y
VERBOSE = N
CROSS_COMPILE = arm-none-eabi-
STFLASH = st-flash
STUTIL = st-util
OPENOCD = openocd
# **************************************************************************** #
# < Makefile guts > #
# **************************************************************************** #
# DON'T CHANGE ANYTHING UNLESS YOU KNOW WHAT YOU'RE DOING #
# **************************************************************************** #
SRCS += $(INIT_SRC)
SRCS += $(OTHER_SRCS)
OBJS = $(addsuffix .o, $(basename $(SRCS)))
SUS = $(addsuffix .su, $(basename $(OBJS)))
CFLAGS += -mcpu=cortex-m3 -mthumb -mabi=aapcs
CFLAGS += -Wall -Wextra
CFLAGS += -fno-common -static
CFLAGS += -ffunction-sections -fdata-sections -Wl,--gc-sections
LDFLAGS += -march=armv7-m -mabi=aapcs
LDFLAGS += -nostartfiles -nostdlib -lgcc
LDFLAGS += -T$(LINKER_SCRIPT)
CC = $(CROSS_COMPILE)gcc
LD = $(CROSS_COMPILE)ld
OBJDUMP = $(CROSS_COMPILE)objdump
OBJCOPY = $(CROSS_COMPILE)objcopy
SIZE = $(CROSS_COMPILE)size
GDB = $(CROSS_COMPILE)gdb
ECHO = echo
RM = rm
ifeq ($(VERBOSE),Y)
SILENCE =
else
SILENCE = @
endif
GDB_PARAM = -quiet --eval-command="target extended-remote localhost:$(STUTIL_PORT)"
.PHONY: all debug build debug_build output info size flash erase server gdb clean_objs clean
all: clean $(SRCS) build clean_objs output size
debug: clean $(SRCS) debug_build info output size
build: COMFLAGS = $(OPTFLAGS)
build: $(TARGET).elf
debug_build: COMFLAGS = $(DBG_OPTFLAGS) -ggdb3
debug_build: CFLAGS += -fstack-usage
debug_build: LDFLAGS += -Xlinker -Map=$(TARGET).map
debug_build: $(TARGET).elf
$(TARGET).elf: $(OBJS)
$(SILENCE)$(CC) $(LDFLAGS) $(COMFLAGS) $(OBJS) -o "$@"
.SECONDARY: $(OBJS)
%.o: %.c
$(SILENCE)$(CC) $(CFLAGS) $(COMFLAGS) -c "$<" -o "$@"
output: $(TARGET).hex $(TARGET).bin
$(TARGET).hex: $(TARGET).elf
$(SILENCE)$(OBJCOPY) -O ihex $< $@
$(TARGET).bin: $(TARGET).elf
$(SILENCE)$(OBJCOPY) -O binary $< $@
info: $(TARGET).elf
$(SILENCE)$(OBJDUMP) -x -S $(TARGET).elf > $(TARGET).lst
$(SILENCE)$(OBJDUMP) -D $(TARGET).elf > $(TARGET).dis
$(SILENCE)$(SIZE) $(TARGET).elf > $(TARGET).size
size: $(TARGET).elf
$(SILENCE)$(SIZE) $(TARGET).elf
flash: $(TARGET).bin
$(OPENOCD) -f /home/ianw/STM/opendps/openocd/scripts/interface/stlink-v2.cfg -f /home/ianw/STM/opendps/openocd/scripts/target/stm32f1x.cfg -c "program $(TARGET).bin verify reset exit 0x8000000"
erase:
$(OPENOCD) -f /home/ianw/STM/opendps/openocd/scripts/interface/stlink-v2.cfg -f /home/ianw/STM/opendps/openocd/scripts/target/stm32f1x.cfg -c "flash erase_address unlock 0x08000000 0x10000"
server: $(TARGET).elf
$(SILENCE)$(ECHO) "On another terminal run \"make gdb\""
$(SILENCE)$(STUTIL) -p $(STUTIL_PORT)
gdb: $(TARGET).elf
$(SILENCE)$(ECHO) "Run \"load\" to start debugging."
$(SILENCE)$(GDB) $(GDB_PARAM) $(TARGET).elf
clean_objs:
ifeq ($(REMOVE_OBJS),Y)
$(SILENCE)$(RM) -f $(OBJS)
endif
clean:
$(SILENCE)$(RM) -f $(TARGET).elf
$(SILENCE)$(RM) -f $(TARGET).bin
$(SILENCE)$(RM) -f $(TARGET).hex
$(SILENCE)$(RM) -f $(TARGET).size
$(SILENCE)$(RM) -f $(TARGET).lst
$(SILENCE)$(RM) -f $(TARGET).dis
$(SILENCE)$(RM) -f $(TARGET).map
$(SILENCE)$(RM) -f $(OBJS)
$(SILENCE)$(RM) -f $(SUS)

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/*
********************************************************************************
* *
* Copyright (c) 2017 Andrea Loi *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included *
* in all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
********************************************************************************
*/
/******************************************************************************/
/* DON'T EDIT THIS FILE UNLESS YOU KNOW WHAT YOU'RE DOING! */
/******************************************************************************/
_heap_size = 0x00000400;
_stack_size = 0x00000400;
_isrvectors_tend = 0x00000150;
ENTRY(ResetHandler)
MEMORY {
FLASH (RX) : ORIGIN = 0x08000000, LENGTH = 0x10000
RAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x05000
}
SECTIONS {
.isrvectors 0x08000000 :
{
_sisrvectors = .;
KEEP(*(.isrvectors))
ASSERT(. == _isrvectors_tend, "The vector table needs to be 84 elements long!");
_eisrvectors = .;
} >FLASH
.text :
{
. = ALIGN(4);
_stext = .;
*(.text*)
*(.rodata*)
. = ALIGN(4);
_etext = .;
} >FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} >FLASH
.ARM : {
*(.ARM.exidx*)
} >FLASH
.data :
{
. = ALIGN(4);
_sdata = .;
*(.data*)
. = ALIGN(4);
_edata = .;
} >RAM AT >FLASH
_ldata = LOADADDR(.data);
.bss :
{
. = ALIGN(4);
_sbss = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
} >RAM
._heap_trick :
{
. = ALIGN(4);
. = . + _heap_size;
. = ALIGN(4);
} >RAM
._stack_trick :
{
. = ALIGN(8);
. = . + _stack_size;
. = ALIGN(8);
} >RAM
}

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/*
********************************************************************************
* *
* Copyright (c) 2017 Andrea Loi *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included *
* in all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
********************************************************************************
* This file contains common code meant to be included in every source file. *
********************************************************************************
*/
#ifndef COMMON_H
#define COMMON_H
// *****************************************************************************
// * < Sized integer types > *
// *****************************************************************************
// * If you're including stdint.h you must remove the lines below. *
// *****************************************************************************
#define int32_t int
#define int16_t short
#define int8_t char
#define uint32_t unsigned int
#define uint16_t unsigned short
#define uint8_t unsigned char
// *****************************************************************************
// * < Bitwise operations > *
// *****************************************************************************
// * BIT_SET(FOO, BIT_4 | BIT_2) -> set bit 4 and 2 of register FOO *
// * BIT_CLR(FOO, BIT_4 | BIT_2) -> clear bit 4 and 2 of register FOO *
// * BIT_CLR_SET(FOO, BIT_1 | BIT_5, BIT_2 | BIT_7) *
// * -> clear bit 1 and 5 and set bit 2 and 7 of register FOO *
// *****************************************************************************
#define BIT_SET(REG, BITSET) ( (REG) |= (BITSET) )
#define BIT_CLR(REG, BITCLR) ( (REG) &= (~(BITCLR)) )
#define BIT_CLR_SET(REG, BITCLR, BITSET) ( (REG) = ( ( (REG) & (~(BITCLR)) ) | (BITSET) ) )
#define BIT_0 0x00000001
#define BIT_1 0x00000002
#define BIT_2 0x00000004
#define BIT_3 0x00000008
#define BIT_4 0x00000010
#define BIT_5 0x00000020
#define BIT_6 0x00000040
#define BIT_7 0x00000080
#define BIT_8 0x00000100
#define BIT_9 0x00000200
#define BIT_10 0x00000400
#define BIT_11 0x00000800
#define BIT_12 0x00001000
#define BIT_13 0x00002000
#define BIT_14 0x00004000
#define BIT_15 0x00008000
#define BIT_16 0x00010000
#define BIT_17 0x00020000
#define BIT_18 0x00040000
#define BIT_19 0x00080000
#define BIT_20 0x00100000
#define BIT_21 0x00200000
#define BIT_22 0x00400000
#define BIT_23 0x00800000
#define BIT_24 0x01000000
#define BIT_25 0x02000000
#define BIT_26 0x04000000
#define BIT_27 0x08000000
#define BIT_28 0x10000000
#define BIT_29 0x20000000
#define BIT_30 0x40000000
#define BIT_31 0x80000000
#define MASK_0 0xFFFFFFFE
#define MASK_1 0xFFFFFFFD
#define MASK_2 0xFFFFFFFB
#define MASK_3 0xFFFFFFF7
#define MASK_4 0xFFFFFFEF
#define MASK_5 0xFFFFFFDF
#define MASK_6 0xFFFFFFBF
#define MASK_7 0xFFFFFF7F
#define MASK_8 0xFFFFFEFF
#define MASK_9 0xFFFFFDFF
#define MASK_10 0xFFFFFBFF
#define MASK_11 0xFFFFF7FF
#define MASK_12 0xFFFFEFFF
#define MASK_13 0xFFFFDFFF
#define MASK_14 0xFFFFBFFF
#define MASK_15 0xFFFF7FFF
#define MASK_16 0xFFFEFFFF
#define MASK_17 0xFFFDFFFF
#define MASK_18 0xFFFBFFFF
#define MASK_19 0xFFF7FFFF
#define MASK_20 0xFFEFFFFF
#define MASK_21 0xFFDFFFFF
#define MASK_22 0xFFBFFFFF
#define MASK_23 0xFF7FFFFF
#define MASK_24 0xFEFFFFFF
#define MASK_25 0xFDFFFFFF
#define MASK_26 0xFBFFFFFF
#define MASK_27 0xF7FFFFFF
#define MASK_28 0xEFFFFFFF
#define MASK_29 0xDFFFFFFF
#define MASK_30 0xBFFFFFFF
#define MASK_31 0x7FFFFFFF
#endif

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/*
********************************************************************************
* *
* Copyright (c) 2017 Andrea Loi *
* *
* Permission is hereby granted, free of charge, to any person obtaining a *
* copy of this software and associated documentation files (the "Software"), *
* to deal in the Software without restriction, including without limitation *
* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
* and/or sell copies of the Software, and to permit persons to whom the *
* Software is furnished to do so, subject to the following conditions: *
* *
* The above copyright notice and this permission notice shall be included *
* in all copies or substantial portions of the Software. *
* *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
* DEALINGS IN THE SOFTWARE. *
* *
********************************************************************************
* This file contains the interrupt vector table and the reset handler code. *
********************************************************************************
*/
#include "common.h"
#include "regs.h"
void ResetHandler(void); // This is the first function to be executed.
void Halt(void); // This function just runs an infinite loop.
extern int main(void); // ResetHandler will call main after initialization.
// *****************************************************************************
// * Define what to do if the cpu receives an interrupt for a peripheral that *
// * doesn't exist. This doesn't make sense and it should never happen. *
// *****************************************************************************
#define ISR_NOT_IMPL ((uint32_t *) Halt)
// *****************************************************************************
// * Define the default interrupt function. *
// *****************************************************************************
#define ISR_NOT_SET ((uint32_t *) Halt)
// *****************************************************************************
// * Define where the stack starts. *
// * ARM Cortex-M CPUs use a Full Descending stack, meaning the stack starts *
// * at the end of the RAM and grows towards the beginning of the RAM. *
// * An STM32F103C8 has 20KB of RAM, from 0x20000000 to 0x20004FFF. *
// * The stack bottom is set to 0x20005000 because the SP register is *
// * decremented BEFORE storing a value, therefore the first byte pushed to *
// * the stack will be at address 0x20004FFF. *
// *****************************************************************************
#define STACK_START_ADDR 0x20005000
// *****************************************************************************
// * Set the vector table and store it in the .isrvectors section. *
// *****************************************************************************
uint32_t (* const vectortable[]) __attribute__ ((section(".isrvectors"))) = {
/* Function Pointer Name Addr IRQn EXn */
(uint32_t *) STACK_START_ADDR, /* SP 0x0000 N/A N/A */
(uint32_t *) ResetHandler, /* Reset 0x0004 N/A 1 */
ISR_NOT_SET, /* NMI 0x0008 -14 2 */
ISR_NOT_SET, /* HardFault 0x000C -13 3 */
ISR_NOT_SET, /* MemManage 0x0010 -12 4 */
ISR_NOT_SET, /* BusFault 0x0014 -11 5 */
ISR_NOT_SET, /* UsageFault 0x0018 -10 6 */
ISR_NOT_IMPL, /* Reserved 0x001C -9 7 */
ISR_NOT_IMPL, /* Reserved 0x0020 -8 8 */
ISR_NOT_IMPL, /* Reserved 0x0024 -7 9 */
ISR_NOT_IMPL, /* Reserved 0x0028 -6 10 */
ISR_NOT_SET, /* SVCall 0x002C -5 11 */
ISR_NOT_SET, /* DebugMonitor 0x0030 -4 12 */
ISR_NOT_IMPL, /* Reserved 0x0034 -3 13 */
ISR_NOT_SET, /* PendSV 0x0038 -2 14 */
ISR_NOT_SET, /* SysTick 0x003C -1 15 */
ISR_NOT_SET, /* WWDG 0x0040 0 16 */
ISR_NOT_SET, /* PVD 0x0044 1 17 */
ISR_NOT_SET, /* TAMPER 0x0048 2 18 */
ISR_NOT_SET, /* RTC 0x004C 3 19 */
ISR_NOT_SET, /* FLASH 0x0050 4 20 */
ISR_NOT_SET, /* RCC 0x0054 5 21 */
ISR_NOT_SET, /* EXTI0 0x0058 6 22 */
ISR_NOT_SET, /* EXTI1 0x005C 7 23 */
ISR_NOT_SET, /* EXTI2 0x0060 8 24 */
ISR_NOT_SET, /* EXTI3 0x0064 9 25 */
ISR_NOT_SET, /* EXTI4 0x0068 10 26 */
ISR_NOT_SET, /* DMA1_Channel1 0x006C 11 27 */
ISR_NOT_SET, /* DMA1_Channel2 0x0070 12 28 */
ISR_NOT_SET, /* DMA1_Channel3 0x0074 13 29 */
ISR_NOT_SET, /* DMA1_Channel4 0x0078 14 30 */
ISR_NOT_SET, /* DMA1_Channel5 0x007C 15 31 */
ISR_NOT_SET, /* DMA1_Channel6 0x0080 16 32 */
ISR_NOT_SET, /* DMA1_Channel7 0x0084 17 33 */
ISR_NOT_SET, /* ADC1_2 0x0088 18 34 */
ISR_NOT_SET, /* USB_HP_CAN_TX 0x008C 19 35 */
ISR_NOT_SET, /* USB_LP_CAN_RX0 0x0090 20 36 */
ISR_NOT_SET, /* CAN_RX1 0x0094 21 37 */
ISR_NOT_SET, /* CAN_SCE 0x0098 22 38 */
ISR_NOT_SET, /* EXTI9_5 0x009C 23 39 */
ISR_NOT_SET, /* TIM1_BRK 0x00A0 24 40 */
ISR_NOT_SET, /* TIM1_UP 0x00A4 25 41 */
ISR_NOT_SET, /* TIM1_TRG_COM 0x00A8 26 42 */
ISR_NOT_SET, /* TIM1_CC 0x00AC 27 43 */
ISR_NOT_SET, /* TIM2 0x00B0 28 44 */
ISR_NOT_SET, /* TIM3 0x00B4 29 45 */
ISR_NOT_SET, /* TIM4 0x00B8 30 46 */
ISR_NOT_SET, /* I2C1_EV 0x00BC 31 47 */
ISR_NOT_SET, /* I2C1_ER 0x00C0 32 48 */
ISR_NOT_SET, /* I2C2_EV 0x00C4 33 49 */
ISR_NOT_SET, /* I2C2_ER 0x00C8 34 50 */
ISR_NOT_SET, /* SPI1 0x00CC 35 51 */
ISR_NOT_SET, /* SPI2 0x00D0 36 52 */
ISR_NOT_SET, /* USART1 0x00D4 37 53 */
ISR_NOT_SET, /* USART2 0x00D8 38 54 */
ISR_NOT_SET, /* USART3 0x00DC 39 55 */
ISR_NOT_SET, /* EXTI15_10 0x00E0 40 56 */
ISR_NOT_SET, /* RTCAlarm 0x00E4 41 57 */
ISR_NOT_SET, /* USBWakeup 0x00E8 42 58 */
ISR_NOT_IMPL, /* TIM8_BRK 0x00EC 43 59 */
ISR_NOT_IMPL, /* TIM8_UP 0x00F0 44 60 */
ISR_NOT_IMPL, /* TIM8_TRG_COM 0x00F4 45 61 */
ISR_NOT_IMPL, /* TIM8_CC 0x00F8 46 62 */
ISR_NOT_IMPL, /* ADC3 0x00FC 47 63 */
ISR_NOT_IMPL, /* FSMC 0x0100 48 64 */
ISR_NOT_IMPL, /* SDIO 0x0104 49 65 */
ISR_NOT_IMPL, /* TIM5 0x0108 50 66 */
ISR_NOT_IMPL, /* SPI3 0x010C 51 67 */
ISR_NOT_IMPL, /* UART4 0x0110 52 68 */
ISR_NOT_IMPL, /* UART5 0x0114 53 69 */
ISR_NOT_IMPL, /* TIM6 0x0118 54 70 */
ISR_NOT_IMPL, /* TIM7 0x011C 55 71 */
ISR_NOT_IMPL, /* DMA2_Channel1 0x0120 56 72 */
ISR_NOT_IMPL, /* DMA2_Channel2 0x0124 57 73 */
ISR_NOT_IMPL, /* DMA2_Channel3 0x0128 58 74 */
ISR_NOT_IMPL, /* DMA2_Channel4 0x012C 59 75 */
ISR_NOT_IMPL, /* DMA2_Channel5 0x0130 60 76 */
ISR_NOT_IMPL, /* ETH 0x0134 61 77 */
ISR_NOT_IMPL, /* ETH_WKUP 0x0138 62 78 */
ISR_NOT_IMPL, /* CAN2_TX 0x013C 63 79 */
ISR_NOT_IMPL, /* CAN2_RX0 0x0140 64 80 */
ISR_NOT_IMPL, /* CAN2_RX1 0x0144 65 81 */
ISR_NOT_IMPL, /* CAN2_SCE 0x0148 66 82 */
ISR_NOT_IMPL /* OTG_FS 0x014C 67 83 */
};
// *****************************************************************************
// * This is the first function that is executed after a reset. *
// * 1. It selects the debug interface. *
// * 2. It sets the stack alignment. *
// * 3. It copies the initialized variables data from flash to RAM. *
// * 4. It clears the uninitialized variables. *
// * 5. It calls main. *
// * 6. It halts if main returns. *
// *****************************************************************************
// * DON'T EDIT THIS FUNCTION UNLESS YOU KNOW WHAT YOU'RE DOING! *
// *****************************************************************************
__attribute__ ((noreturn)) void ResetHandler(void){
extern char _sdata; // .data section start
extern char _edata; // .data section end
extern char _sbss; // .bss section start
extern char _ebss; // .bss section end
extern char _ldata; // .data load address
char *dst = &_sdata;
char *src = &_ldata;
// enable 8-byte stack alignment to comply with AAPCS
BIT_SET(SCB->CCR, BIT_9);
// copy initialized variables data
while ( dst < &_edata ) { *dst++ = *src++; }
// clear uninitialized variables
for ( dst = &_sbss; dst < &_ebss; dst++ ) { *dst = 0; }
// call main
main();
// halt
for(;;) {}
}
// *****************************************************************************
// * Halt the program. *
// *****************************************************************************
__attribute__ ((noreturn)) void Halt(void){
for(;;) {}
}

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#include "common.h"
#include "regs.h"
// PA01 - Indicator LED
// PA04 - NSS
// PA05 - SCK
// PA06 - MISO
// PA07 - MOSI
// PA08 - Test Push Switch
// PA11 - LD
void Delay(uint32_t);
uint8_t SendReceiveSPIByte(uint32_t);
void SendSPIData (uint8_t,uint32_t);
int main(void)
{
// Below are the ADF4350 settings for a 1 GHz -4dBm output
uint32_t ar0=0x00500000;
uint32_t ar1=0x08008011;
uint32_t ar2=0x00004e42;
uint32_t ar3=0x000004b3;
uint32_t ar4=0x00ac8024;
uint32_t ar5=0x00580005;
// Turn on the port A + SPI1 clocks
*(uint32_t *)(RCC_BASE + 0x18) &= MASK_2 | MASK_12;
*(uint32_t *)(RCC_BASE + 0x18) |= BIT_2 | BIT_12;
// SPI_CR2 setup
// 02 SSOE enabled so SS output is enabled in master mode
*(uint32_t *)(SPI1_BASE + 0x04) &= MASK_2;
*(uint32_t *)(SPI1_BASE + 0x04) |= BIT_2;
// I/O
// PA01 needs to be in push pull mode thus 0 turns on the LED and 1 turns it off (0x2) - Bits
// PA04 (SPI NSS) needs to be in alternate push pull mode (0xa) 0b1010
// PA05 (SPI SCK) needs to be in alternate push pull mode (0xa)
// PA06 (SPI MISO) is a floating input (0x4)
// PA07 (SPI MOSI) needs to be in alternate push pull mode (0xa)
*(uint32_t *)GPIOA_BASE &= 0x0000ff0f;
*(uint32_t *)GPIOA_BASE |= 0xa4aa0020;
// PA08 is a push switch input
// PA11 is a floating input
*(uint32_t *)(GPIOA_BASE + 0x04) &= 0xffff0ff0;
*(uint32_t *)(GPIOA_BASE + 0x04) |= 0x00004008;
// PA8 input pull up set P8ODR to 1
// PA6 input pull up set P6ODR to 1
*(uint32_t *)(GPIOA_BASE + 0x0c) &= MASK_8 | MASK_6;
*(uint32_t *)(GPIOA_BASE + 0x0c) |= BIT_8 | BIT_6;
// SPI_CR1 setup
// 15 BIDIMODE 0 - bidirectional
// 14 BIDIOE 0 - output enabled
// 13 CRCEN 0 - CRC disabled
// 12 CRCNEXT 0 - No CRC phase
// 11 DFF 0 - 8 bit data frame
// 10 RXONLY 0 - Full duplex
// 09 SSM 0 - Software slave management enabled
// 08 SSI 0
// 07 LSBFIRST 0 - MSB sent first
// 06 SPE 1 - SPI enabled
// 05/04/03 111 - fpCLK/256
// 02 MSTR 1 - Master
// 01 CPOL 0 - Clock to zero when idle
// 00 CPHA 0 - First clock transition is the data edge
*(uint32_t *)(SPI1_BASE) &= 0xffff0000;
*(uint32_t *)(SPI1_BASE) |= BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2;
// Flash the LED to show everything works
*(uint32_t *)(GPIOA_BASE + 0x14) = BIT_1;
Delay(500000);
*(uint32_t *)(GPIOA_BASE + 0x10) = BIT_1;
Delay(100000);
while (1)
{
// Send the setup data to the synth board
SendSPIData(0,ar0);
SendSPIData(1,ar1);
SendSPIData(2,ar2);
SendSPIData(3,ar3);
SendSPIData(4,ar4);
SendSPIData(5,ar5);
}
// Go into an endless loop waiting for frequency lock to be achieved
while(1)
{
// Read GPIO port A
uint32_t portA = *(uint32_t *)(GPIOA_BASE + 0x08);
// Just bit 11
portA &= BIT_11;
// If we have lock turn on the LED
if (portA == 0) *(uint32_t *)(GPIOA_BASE + 0x10) = BIT_1;
else *(uint32_t *)(GPIOA_BASE + 0x14) = BIT_1;
}
}
// A general purpose delay
void Delay(uint32_t tmax)
{
uint32_t i;
for (i=0;i < tmax ; i++)
{
asm("nop");
}
}
uint8_t SendReceiveSPIByte(uint32_t value)
{
uint8_t lout = 0;
// Put the 8 bits to be sent into the SPI data register
*(uint32_t *)(SPI1_BASE + 0x0c) = value;
// Read a byte
uint8_t inbyte = *(uint32_t *)(SPI1_BASE + 0x0c);
// Loop while the SPI BSY flag is high
while (lout == 0)
{
// Read the SPI status register
uint32_t statusSPI = *(uint32_t *)(SPI1_BASE + 0x08);
// Just bit 1 the transmit buffer empty flag - wait for this to go high then leave this function
statusSPI &= BIT_1;
if (statusSPI == BIT_1) lout = 1;
}
return inbyte;
}
void SendSPIData (uint8_t regNo,uint32_t outval)
{
SendReceiveSPIByte(0xa0);
}

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