1079 lines
33 KiB
C
1079 lines
33 KiB
C
/*
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********************************************************************************
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* *
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* Copyright (c) 2017 Andrea Loi *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining a *
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* copy of this software and associated documentation files (the "Software"), *
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* to deal in the Software without restriction, including without limitation *
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* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
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* and/or sell copies of the Software, and to permit persons to whom the *
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* Software is furnished to do so, subject to the following conditions: *
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* *
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* The above copyright notice and this permission notice shall be included *
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* in all copies or substantial portions of the Software. *
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
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* DEALINGS IN THE SOFTWARE. *
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* *
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********************************************************************************
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* This file defines all the registers. *
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********************************************************************************
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*/
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#ifndef REGS_H
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#define REGS_H
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#include "common.h"
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// *****************************************************************************
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// * DON'T EDIT THIS FILE UNLESS YOU KNOW WHAT YOU'RE DOING! *
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// *****************************************************************************
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// *****************************************************************************
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// * < Register structures > *
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// *****************************************************************************
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typedef struct {
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volatile uint16_t F_SIZE;
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volatile uint16_t RESERVED_1[3];
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volatile uint16_t U_ID_15_0;
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volatile uint16_t U_ID_31_16;
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volatile uint16_t U_ID_63_48;
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volatile uint16_t U_ID_47_32;
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volatile uint16_t U_ID_95_80;
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volatile uint16_t U_ID_79_64;
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} SIG_Type;
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typedef struct {
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volatile uint32_t CR1;
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volatile uint32_t CR2;
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volatile uint32_t SMCR;
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volatile uint32_t DIER;
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volatile uint32_t SR;
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volatile uint32_t EGR;
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volatile uint32_t CCMR1;
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volatile uint32_t CCMR2;
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volatile uint32_t CCER;
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volatile uint32_t CNT;
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volatile uint32_t PSC;
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volatile uint32_t ARR;
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volatile uint32_t RESERVED_1;
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volatile uint32_t CCR1;
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volatile uint32_t CCR2;
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volatile uint32_t CCR3;
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volatile uint32_t CCR4;
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volatile uint32_t RESERVED_2;
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volatile uint32_t DCR;
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volatile uint32_t DMAR;
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} TIM2_Type;
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typedef struct {
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volatile uint32_t CRH;
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volatile uint32_t CRL;
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volatile uint32_t PRLH;
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volatile uint32_t PRLL;
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volatile uint32_t DIVH;
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volatile uint32_t DIVL;
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volatile uint32_t CNTH;
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volatile uint32_t CNTL;
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volatile uint32_t ALRH;
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volatile uint32_t ALRL;
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} RTC_Type;
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typedef struct {
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volatile uint32_t CR;
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volatile uint32_t CFR;
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volatile uint32_t SR;
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} WWDG_Type;
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typedef struct {
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volatile uint32_t KR;
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volatile uint32_t PR;
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volatile uint32_t RLR;
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volatile uint32_t SR;
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} IWDG_Type;
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typedef struct {
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volatile uint32_t CR1;
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volatile uint32_t CR2;
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volatile uint32_t SR;
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volatile uint32_t DR;
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volatile uint32_t CRCPR;
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volatile uint32_t RXCRCR;
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volatile uint32_t TXCRCR;
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volatile uint32_t I2SCFGR;
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volatile uint32_t I2SPR;
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} SPI1_Type;
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typedef struct {
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volatile uint32_t SR;
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volatile uint32_t DR;
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volatile uint32_t BRR;
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volatile uint32_t CR1;
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volatile uint32_t CR2;
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volatile uint32_t CR3;
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volatile uint32_t GTPR;
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} USART1_Type;
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typedef struct {
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volatile uint32_t CR1;
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volatile uint32_t CR2;
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volatile uint32_t OAR1;
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volatile uint32_t OAR2;
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volatile uint32_t DR;
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volatile uint32_t SR1;
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volatile uint32_t SR2;
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volatile uint32_t CCR;
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volatile uint32_t TRISE;
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} I2C1_Type;
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typedef struct {
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volatile uint32_t EP0R;
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volatile uint32_t EP1R;
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volatile uint32_t EP2R;
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volatile uint32_t EP3R;
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volatile uint32_t EP4R;
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volatile uint32_t EP5R;
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volatile uint32_t EP6R;
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volatile uint32_t EP7R;
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volatile uint32_t RESERVED_1[8];
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volatile uint32_t CNTR;
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volatile uint32_t ISTR;
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volatile uint32_t FNR;
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volatile uint32_t DADDR;
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volatile uint32_t BTABLE;
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} USB_Type;
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typedef struct {
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volatile uint32_t CAN_MCR;
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volatile uint32_t CAN_MSR;
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volatile uint32_t CAN_TSR;
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volatile uint32_t CAN_RF0R;
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volatile uint32_t CAN_RF1R;
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volatile uint32_t CAN_IER;
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volatile uint32_t CAN_ESR;
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volatile uint32_t CAN_BTR;
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volatile uint32_t RESERVED_1[88];
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volatile uint32_t CAN_TI0R;
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volatile uint32_t CAN_TDT0R;
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volatile uint32_t CAN_TDL0R;
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volatile uint32_t CAN_TDH0R;
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volatile uint32_t CAN_TI1R;
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volatile uint32_t CAN_TDT1R;
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volatile uint32_t CAN_TDL1R;
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volatile uint32_t CAN_TDH1R;
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volatile uint32_t CAN_TI2R;
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volatile uint32_t CAN_TDT2R;
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volatile uint32_t CAN_TDL2R;
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volatile uint32_t CAN_TDH2R;
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volatile uint32_t CAN_RI0R;
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volatile uint32_t CAN_RDT0R;
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volatile uint32_t CAN_RDL0R;
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volatile uint32_t CAN_RDH0R;
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volatile uint32_t CAN_RI1R;
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volatile uint32_t CAN_RDT1R;
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volatile uint32_t CAN_RDL1R;
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volatile uint32_t CAN_RDH1R;
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volatile uint32_t RESERVED_2[12];
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volatile uint32_t CAN_FMR;
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volatile uint32_t CAN_FM1R;
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volatile uint32_t RESERVED_3;
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volatile uint32_t CAN_FS1R;
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volatile uint32_t RESERVED_4;
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volatile uint32_t CAN_FFA1R;
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volatile uint32_t RESERVED_5;
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volatile uint32_t CAN_FA1R;
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volatile uint32_t RESERVED_6[8];
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volatile uint32_t F0R1;
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volatile uint32_t F0R2;
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volatile uint32_t F1R1;
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volatile uint32_t F1R2;
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volatile uint32_t F2R1;
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volatile uint32_t F2R2;
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volatile uint32_t F3R1;
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volatile uint32_t F3R2;
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volatile uint32_t F4R1;
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volatile uint32_t F4R2;
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volatile uint32_t F5R1;
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volatile uint32_t F5R2;
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volatile uint32_t F6R1;
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volatile uint32_t F6R2;
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volatile uint32_t F7R1;
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volatile uint32_t F7R2;
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volatile uint32_t F8R1;
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volatile uint32_t F8R2;
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volatile uint32_t F9R1;
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volatile uint32_t F9R2;
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volatile uint32_t F10R1;
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volatile uint32_t F10R2;
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volatile uint32_t F11R1;
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volatile uint32_t F11R2;
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volatile uint32_t F12R1;
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volatile uint32_t F12R2;
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volatile uint32_t F13R1;
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volatile uint32_t F13R2;
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} CAN1_Type;
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typedef struct {
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volatile uint32_t DR1;
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volatile uint32_t DR2;
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volatile uint32_t DR3;
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volatile uint32_t DR4;
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volatile uint32_t DR5;
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volatile uint32_t DR6;
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volatile uint32_t DR7;
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volatile uint32_t DR8;
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volatile uint32_t DR9;
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volatile uint32_t DR10;
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volatile uint32_t RTCCR;
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volatile uint32_t CR;
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volatile uint32_t CSR;
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volatile uint32_t RESERVED_1[2];
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volatile uint32_t DR11;
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volatile uint32_t DR12;
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volatile uint32_t DR13;
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volatile uint32_t DR14;
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volatile uint32_t DR15;
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volatile uint32_t DR16;
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volatile uint32_t DR17;
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volatile uint32_t DR18;
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volatile uint32_t DR19;
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volatile uint32_t DR20;
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volatile uint32_t DR21;
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volatile uint32_t DR22;
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volatile uint32_t DR23;
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volatile uint32_t DR24;
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volatile uint32_t DR25;
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volatile uint32_t DR26;
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volatile uint32_t DR27;
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volatile uint32_t DR28;
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volatile uint32_t DR29;
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volatile uint32_t DR30;
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volatile uint32_t DR31;
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volatile uint32_t DR32;
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volatile uint32_t DR33;
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volatile uint32_t DR34;
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volatile uint32_t DR35;
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volatile uint32_t DR36;
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volatile uint32_t DR37;
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volatile uint32_t DR38;
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volatile uint32_t DR39;
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volatile uint32_t DR40;
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volatile uint32_t DR41;
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volatile uint32_t DR42;
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} BKP_Type;
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typedef struct {
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volatile uint32_t CR;
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volatile uint32_t CSR;
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} PWR_Type;
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typedef struct {
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volatile uint32_t EVCR;
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volatile uint32_t MAPR;
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volatile uint32_t EXTICR1;
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volatile uint32_t EXTICR2;
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volatile uint32_t EXTICR3;
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volatile uint32_t EXTICR4;
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volatile uint32_t RESERVED_1;
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volatile uint32_t MAPR2;
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} AFIO_Type;
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typedef struct {
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volatile uint32_t IMR;
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volatile uint32_t EMR;
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volatile uint32_t RTSR;
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volatile uint32_t FTSR;
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volatile uint32_t SWIER;
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volatile uint32_t PR;
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} EXTI_Type;
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typedef struct {
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volatile uint32_t CRL;
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volatile uint32_t CRH;
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volatile uint32_t IDR;
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volatile uint32_t ODR;
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volatile uint32_t BSRR;
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volatile uint32_t BRR;
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volatile uint32_t LCKR;
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} GPIOA_Type;
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typedef struct {
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volatile uint32_t SR;
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volatile uint32_t CR1;
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volatile uint32_t CR2;
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volatile uint32_t SMPR1;
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volatile uint32_t SMPR2;
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volatile uint32_t JOFR1;
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volatile uint32_t JOFR2;
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volatile uint32_t JOFR3;
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volatile uint32_t JOFR4;
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volatile uint32_t HTR;
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volatile uint32_t LTR;
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volatile uint32_t SQR1;
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volatile uint32_t SQR2;
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volatile uint32_t SQR3;
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volatile uint32_t JSQR;
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volatile uint32_t JDR1;
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volatile uint32_t JDR2;
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volatile uint32_t JDR3;
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volatile uint32_t JDR4;
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volatile uint32_t DR;
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} ADC1_Type;
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typedef struct {
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volatile uint32_t SR;
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volatile uint32_t CR1;
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volatile uint32_t CR2;
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volatile uint32_t SMPR1;
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volatile uint32_t SMPR2;
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volatile uint32_t JOFR1;
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volatile uint32_t JOFR2;
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volatile uint32_t JOFR3;
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volatile uint32_t JOFR4;
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volatile uint32_t HTR;
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volatile uint32_t LTR;
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volatile uint32_t SQR1;
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volatile uint32_t SQR2;
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volatile uint32_t SQR3;
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volatile uint32_t JSQR;
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volatile uint32_t JDR1;
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volatile uint32_t JDR2;
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volatile uint32_t JDR3;
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volatile uint32_t JDR4;
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volatile uint32_t DR;
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} ADC2_Type;
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typedef struct {
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volatile uint32_t CR1;
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volatile uint32_t CR2;
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volatile uint32_t SMCR;
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volatile uint32_t DIER;
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volatile uint32_t SR;
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volatile uint32_t EGR;
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volatile uint32_t CCMR1;
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volatile uint32_t CCMR2;
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volatile uint32_t CCER;
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volatile uint32_t CNT;
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volatile uint32_t PSC;
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volatile uint32_t ARR;
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volatile uint32_t RCR;
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volatile uint32_t CCR1;
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volatile uint32_t CCR2;
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volatile uint32_t CCR3;
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volatile uint32_t CCR4;
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volatile uint32_t BDTR;
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volatile uint32_t DCR;
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volatile uint32_t DMAR;
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} TIM1_Type;
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typedef struct {
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volatile uint32_t ISR;
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volatile uint32_t IFCR;
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volatile uint32_t CCR1;
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volatile uint32_t CNDTR1;
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volatile uint32_t CPAR1;
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volatile uint32_t CMAR1;
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volatile uint32_t RESERVED_1;
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volatile uint32_t CCR2;
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volatile uint32_t CNDTR2;
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volatile uint32_t CPAR2;
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volatile uint32_t CMAR2;
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volatile uint32_t RESERVED_2;
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volatile uint32_t CCR3;
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volatile uint32_t CNDTR3;
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volatile uint32_t CPAR3;
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volatile uint32_t CMAR3;
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volatile uint32_t RESERVED_3;
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volatile uint32_t CCR4;
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volatile uint32_t CNDTR4;
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volatile uint32_t CPAR4;
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volatile uint32_t CMAR4;
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volatile uint32_t RESERVED_4;
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volatile uint32_t CCR5;
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volatile uint32_t CNDTR5;
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volatile uint32_t CPAR5;
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volatile uint32_t CMAR5;
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volatile uint32_t RESERVED_5;
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volatile uint32_t CCR6;
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volatile uint32_t CNDTR6;
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volatile uint32_t CPAR6;
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volatile uint32_t CMAR6;
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volatile uint32_t RESERVED_6;
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volatile uint32_t CCR7;
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volatile uint32_t CNDTR7;
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volatile uint32_t CPAR7;
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volatile uint32_t CMAR7;
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} DMA1_Type;
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typedef struct {
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volatile uint32_t CR;
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volatile uint32_t CFGR;
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volatile uint32_t CIR;
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volatile uint32_t APB2RSTR;
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volatile uint32_t APB1RSTR;
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volatile uint32_t AHBENR;
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volatile uint32_t APB2ENR;
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volatile uint32_t APB1ENR;
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volatile uint32_t BDCR;
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volatile uint32_t CSR;
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} RCC_Type;
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typedef struct {
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volatile uint32_t ACR;
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volatile uint32_t KEYR;
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volatile uint32_t OPTKEYR;
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volatile uint32_t SR;
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volatile uint32_t CR;
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volatile uint32_t AR;
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volatile uint32_t RESERVED_1;
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volatile uint32_t OBR;
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volatile uint32_t WRPR;
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} FLASH_Type;
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typedef struct {
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volatile uint32_t DR;
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volatile uint32_t IDR;
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volatile uint32_t CR;
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} CRC_Type;
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typedef struct {
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volatile uint32_t RESERVED_1;
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volatile uint32_t ICTR;
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volatile uint32_t RESERVED_2[62];
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volatile uint32_t ISER0;
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volatile uint32_t ISER1;
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volatile uint32_t RESERVED_3[30];
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volatile uint32_t ICER0;
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volatile uint32_t ICER1;
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volatile uint32_t RESERVED_4[30];
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volatile uint32_t ISPR0;
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volatile uint32_t ISPR1;
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volatile uint32_t RESERVED_5[30];
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volatile uint32_t ICPR0;
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volatile uint32_t ICPR1;
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volatile uint32_t RESERVED_6[30];
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volatile uint32_t IABR0;
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volatile uint32_t IABR1;
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volatile uint32_t RESERVED_7[62];
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volatile uint32_t IPR0;
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volatile uint32_t IPR1;
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volatile uint32_t IPR2;
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volatile uint32_t IPR3;
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volatile uint32_t IPR4;
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volatile uint32_t IPR5;
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volatile uint32_t IPR6;
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volatile uint32_t IPR7;
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volatile uint32_t IPR8;
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volatile uint32_t IPR9;
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volatile uint32_t IPR10;
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volatile uint32_t IPR11;
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volatile uint32_t IPR12;
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volatile uint32_t IPR13;
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volatile uint32_t IPR14;
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volatile uint32_t RESERVED_8[689];
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volatile uint32_t STIR;
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} NVIC_Type;
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typedef struct {
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volatile uint32_t CTRL;
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volatile uint32_t LOAD;
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volatile uint32_t VAL;
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volatile uint32_t CALIB;
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} STK_Type;
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typedef struct {
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volatile uint32_t CPUID;
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volatile uint32_t ICSR;
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volatile uint32_t VTOR;
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volatile uint32_t AIRCR;
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volatile uint32_t SCR;
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volatile uint32_t CCR;
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volatile uint32_t SHPR1;
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volatile uint32_t SHPR2;
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volatile uint32_t SHPR3;
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volatile uint32_t SHCRS;
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volatile uint32_t CFSR;
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volatile uint32_t HFSR;
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volatile uint32_t RESERVED_1;
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volatile uint32_t MMAR;
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volatile uint32_t BFAR;
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} SCB_Type;
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typedef struct {
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volatile uint32_t IDCODE;
|
|
volatile uint32_t CR;
|
|
} DBG_Type;
|
|
|
|
|
|
|
|
// *****************************************************************************
|
|
// * < Register base addresses > *
|
|
// *****************************************************************************
|
|
|
|
#define SIG_BASE ((uint32_t) 0x1FFFF7E0)
|
|
#define TIM2_BASE ((uint32_t) 0x40000000)
|
|
#define TIM3_BASE ((uint32_t) 0x40000400)
|
|
#define TIM4_BASE ((uint32_t) 0x40000800)
|
|
#define RTC_BASE ((uint32_t) 0x40002800)
|
|
#define WWDG_BASE ((uint32_t) 0x40002C00)
|
|
#define IWDG_BASE ((uint32_t) 0x40003000)
|
|
#define SPI2_BASE ((uint32_t) 0x40003800)
|
|
#define USART2_BASE ((uint32_t) 0x40004400)
|
|
#define USART3_BASE ((uint32_t) 0x40004800)
|
|
#define I2C1_BASE ((uint32_t) 0x40005400)
|
|
#define I2C2_BASE ((uint32_t) 0x40005800)
|
|
#define USB_BASE ((uint32_t) 0x40005C00)
|
|
#define CAN1_BASE ((uint32_t) 0x40006400)
|
|
#define BKP_BASE ((uint32_t) 0x40006C00)
|
|
#define PWR_BASE ((uint32_t) 0x40007000)
|
|
#define AFIO_BASE ((uint32_t) 0x40010000)
|
|
#define EXTI_BASE ((uint32_t) 0x40010400)
|
|
#define GPIOA_BASE ((uint32_t) 0x40010800)
|
|
#define GPIOB_BASE ((uint32_t) 0x40010C00)
|
|
#define GPIOC_BASE ((uint32_t) 0x40011000)
|
|
#define GPIOD_BASE ((uint32_t) 0x40011400)
|
|
#define ADC1_BASE ((uint32_t) 0x40012400)
|
|
#define ADC2_BASE ((uint32_t) 0x40012800)
|
|
#define TIM1_BASE ((uint32_t) 0x40012C00)
|
|
#define SPI1_BASE ((uint32_t) 0x40013000)
|
|
#define USART1_BASE ((uint32_t) 0x40013800)
|
|
#define DMA1_BASE ((uint32_t) 0x40020000)
|
|
#define RCC_BASE ((uint32_t) 0x40021000)
|
|
#define FLASH_BASE ((uint32_t) 0x40022000)
|
|
#define CRC_BASE ((uint32_t) 0x40023000)
|
|
#define NVIC_BASE ((uint32_t) 0xE000E000)
|
|
#define STK_BASE ((uint32_t) 0xE000E010)
|
|
#define SCB_BASE ((uint32_t) 0xE000ED00)
|
|
#define DBG_BASE ((uint32_t) 0xE0042000)
|
|
|
|
|
|
|
|
// *****************************************************************************
|
|
// * < Register locations assignment > *
|
|
// *****************************************************************************
|
|
|
|
#define SIG ( (SIG_Type*) SIG_BASE )
|
|
#define TIM2 ( (TIM2_Type*) TIM2_BASE )
|
|
#define TIM3 ( (TIM2_Type*) TIM3_BASE )
|
|
#define TIM4 ( (TIM2_Type*) TIM4_BASE )
|
|
#define RTC ( (RTC_Type*) RTC_BASE )
|
|
#define WWDG ( (WWDG_Type*) WWDG_BASE )
|
|
#define IWDG ( (IWDG_Type*) IWDG_BASE )
|
|
#define SPI2 ( (SPI1_Type*) SPI2_BASE )
|
|
#define USART2 ( (USART1_Type*) USART2_BASE )
|
|
#define USART3 ( (USART1_Type*) USART3_BASE )
|
|
#define I2C1 ( (I2C1_Type*) I2C1_BASE )
|
|
#define I2C2 ( (I2C1_Type*) I2C2_BASE )
|
|
#define USB ( (USB_Type*) USB_BASE )
|
|
#define CAN1 ( (CAN1_Type*) CAN1_BASE )
|
|
#define BKP ( (BKP_Type*) BKP_BASE )
|
|
#define PWR ( (PWR_Type*) PWR_BASE )
|
|
#define AFIO ( (AFIO_Type*) AFIO_BASE )
|
|
#define EXTI ( (EXTI_Type*) EXTI_BASE )
|
|
#define GPIOA ( (GPIOA_Type*) GPIOA_BASE )
|
|
#define GPIOB ( (GPIOA_Type*) GPIOB_BASE )
|
|
#define GPIOC ( (GPIOA_Type*) GPIOC_BASE )
|
|
#define GPIOD ( (GPIOA_Type*) GPIOD_BASE )
|
|
#define ADC1 ( (ADC1_Type*) ADC1_BASE )
|
|
#define ADC2 ( (ADC2_Type*) ADC2_BASE )
|
|
#define TIM1 ( (TIM1_Type*) TIM1_BASE )
|
|
#define SPI1 ( (SPI1_Type*) SPI1_BASE )
|
|
#define USART1 ( (USART1_Type*) USART1_BASE )
|
|
#define DMA1 ( (DMA1_Type*) DMA1_BASE )
|
|
#define RCC ( (RCC_Type*) RCC_BASE )
|
|
#define FLASH ( (FLASH_Type*) FLASH_BASE )
|
|
#define CRC ( (CRC_Type*) CRC_BASE )
|
|
#define NVIC ( (NVIC_Type*) NVIC_BASE )
|
|
#define STK ( (STK_Type*) STK_BASE )
|
|
#define SCB ( (SCB_Type*) SCB_BASE )
|
|
#define DBG ( (DBG_Type*) DBG_BASE )
|
|
|
|
|
|
|
|
// *****************************************************************************
|
|
// * < Bit-banding register structures > *
|
|
// *****************************************************************************
|
|
|
|
typedef struct {
|
|
volatile uint32_t CR1[32];
|
|
volatile uint32_t CR2[32];
|
|
volatile uint32_t SMCR[32];
|
|
volatile uint32_t DIER[32];
|
|
volatile uint32_t SR[32];
|
|
volatile uint32_t EGR[32];
|
|
volatile uint32_t CCMR1[32];
|
|
volatile uint32_t CCMR2[32];
|
|
volatile uint32_t CCER[32];
|
|
volatile uint32_t CNT[32];
|
|
volatile uint32_t PSC[32];
|
|
volatile uint32_t ARR[32];
|
|
volatile uint32_t RESERVED_1[32];
|
|
volatile uint32_t CCR1[32];
|
|
volatile uint32_t CCR2[32];
|
|
volatile uint32_t CCR3[32];
|
|
volatile uint32_t CCR4[32];
|
|
volatile uint32_t RESERVED_2[32];
|
|
volatile uint32_t DCR[32];
|
|
volatile uint32_t DMAR[32];
|
|
} TIM2_BB_Type;
|
|
|
|
typedef struct {
|
|
volatile uint32_t CRH[32];
|
|
volatile uint32_t CRL[32];
|
|
volatile uint32_t PRLH[32];
|
|
volatile uint32_t PRLL[32];
|
|
volatile uint32_t DIVH[32];
|
|
volatile uint32_t DIVL[32];
|
|
volatile uint32_t CNTH[32];
|
|
volatile uint32_t CNTL[32];
|
|
volatile uint32_t ALRH[32];
|
|
volatile uint32_t ALRL[32];
|
|
} RTC_BB_Type;
|
|
|
|
typedef struct {
|
|
volatile uint32_t CR[32];
|
|
volatile uint32_t CFR[32];
|
|
volatile uint32_t SR[32];
|
|
} WWDG_BB_Type;
|
|
|
|
typedef struct {
|
|
volatile uint32_t KR[32];
|
|
volatile uint32_t PR[32];
|
|
volatile uint32_t RLR[32];
|
|
volatile uint32_t SR[32];
|
|
} IWDG_BB_Type;
|
|
|
|
typedef struct {
|
|
volatile uint32_t CR1[32];
|
|
volatile uint32_t CR2[32];
|
|
volatile uint32_t SR[32];
|
|
volatile uint32_t DR[32];
|
|
volatile uint32_t CRCPR[32];
|
|
volatile uint32_t RXCRCR[32];
|
|
volatile uint32_t TXCRCR[32];
|
|
volatile uint32_t I2SCFGR[32];
|
|
volatile uint32_t I2SPR[32];
|
|
} SPI1_BB_Type;
|
|
|
|
typedef struct {
|
|
volatile uint32_t SR[32];
|
|
volatile uint32_t DR[32];
|
|
volatile uint32_t BRR[32];
|
|
volatile uint32_t CR1[32];
|
|
volatile uint32_t CR2[32];
|
|
volatile uint32_t CR3[32];
|
|
volatile uint32_t GTPR[32];
|
|
} USART1_BB_Type;
|
|
|
|
typedef struct {
|
|
volatile uint32_t CR1[32];
|
|
volatile uint32_t CR2[32];
|
|
volatile uint32_t OAR1[32];
|
|
volatile uint32_t OAR2[32];
|
|
volatile uint32_t DR[32];
|
|
volatile uint32_t SR1[32];
|
|
volatile uint32_t SR2[32];
|
|
volatile uint32_t CCR[32];
|
|
volatile uint32_t TRISE[32];
|
|
} I2C1_BB_Type;
|
|
|
|
typedef struct {
|
|
volatile uint32_t EP0R[32];
|
|
volatile uint32_t EP1R[32];
|
|
volatile uint32_t EP2R[32];
|
|
volatile uint32_t EP3R[32];
|
|
volatile uint32_t EP4R[32];
|
|
volatile uint32_t EP5R[32];
|
|
volatile uint32_t EP6R[32];
|
|
volatile uint32_t EP7R[32];
|
|
volatile uint32_t RESERVED_1[8][32];
|
|
volatile uint32_t CNTR[32];
|
|
volatile uint32_t ISTR[32];
|
|
volatile uint32_t FNR[32];
|
|
volatile uint32_t DADDR[32];
|
|
volatile uint32_t BTABLE[32];
|
|
} USB_BB_Type;
|
|
|
|
typedef struct {
|
|
volatile uint32_t CAN_MCR[32];
|
|
volatile uint32_t CAN_MSR[32];
|
|
volatile uint32_t CAN_TSR[32];
|
|
volatile uint32_t CAN_RF0R[32];
|
|
volatile uint32_t CAN_RF1R[32];
|
|
volatile uint32_t CAN_IER[32];
|
|
volatile uint32_t CAN_ESR[32];
|
|
volatile uint32_t CAN_BTR[32];
|
|
volatile uint32_t RESERVED_1[88][32];
|
|
volatile uint32_t CAN_TI0R[32];
|
|
volatile uint32_t CAN_TDT0R[32];
|
|
volatile uint32_t CAN_TDL0R[32];
|
|
volatile uint32_t CAN_TDH0R[32];
|
|
volatile uint32_t CAN_TI1R[32];
|
|
volatile uint32_t CAN_TDT1R[32];
|
|
volatile uint32_t CAN_TDL1R[32];
|
|
volatile uint32_t CAN_TDH1R[32];
|
|
volatile uint32_t CAN_TI2R[32];
|
|
volatile uint32_t CAN_TDT2R[32];
|
|
volatile uint32_t CAN_TDL2R[32];
|
|
volatile uint32_t CAN_TDH2R[32];
|
|
volatile uint32_t CAN_RI0R[32];
|
|
volatile uint32_t CAN_RDT0R[32];
|
|
volatile uint32_t CAN_RDL0R[32];
|
|
volatile uint32_t CAN_RDH0R[32];
|
|
volatile uint32_t CAN_RI1R[32];
|
|
volatile uint32_t CAN_RDT1R[32];
|
|
volatile uint32_t CAN_RDL1R[32];
|
|
volatile uint32_t CAN_RDH1R[32];
|
|
volatile uint32_t RESERVED_2[12][32];
|
|
volatile uint32_t CAN_FMR[32];
|
|
volatile uint32_t CAN_FM1R[32];
|
|
volatile uint32_t RESERVED_3[32];
|
|
volatile uint32_t CAN_FS1R[32];
|
|
volatile uint32_t RESERVED_4[32];
|
|
volatile uint32_t CAN_FFA1R[32];
|
|
volatile uint32_t RESERVED_5[32];
|
|
volatile uint32_t CAN_FA1R[32];
|
|
volatile uint32_t RESERVED_6[8][32];
|
|
volatile uint32_t F0R1[32];
|
|
volatile uint32_t F0R2[32];
|
|
volatile uint32_t F1R1[32];
|
|
volatile uint32_t F1R2[32];
|
|
volatile uint32_t F2R1[32];
|
|
volatile uint32_t F2R2[32];
|
|
volatile uint32_t F3R1[32];
|
|
volatile uint32_t F3R2[32];
|
|
volatile uint32_t F4R1[32];
|
|
volatile uint32_t F4R2[32];
|
|
volatile uint32_t F5R1[32];
|
|
volatile uint32_t F5R2[32];
|
|
volatile uint32_t F6R1[32];
|
|
volatile uint32_t F6R2[32];
|
|
volatile uint32_t F7R1[32];
|
|
volatile uint32_t F7R2[32];
|
|
volatile uint32_t F8R1[32];
|
|
volatile uint32_t F8R2[32];
|
|
volatile uint32_t F9R1[32];
|
|
volatile uint32_t F9R2[32];
|
|
volatile uint32_t F10R1[32];
|
|
volatile uint32_t F10R2[32];
|
|
volatile uint32_t F11R1[32];
|
|
volatile uint32_t F11R2[32];
|
|
volatile uint32_t F12R1[32];
|
|
volatile uint32_t F12R2[32];
|
|
volatile uint32_t F13R1[32];
|
|
volatile uint32_t F13R2[32];
|
|
} CAN1_BB_Type;
|
|
|
|
typedef struct {
|
|
volatile uint32_t DR1[32];
|
|
volatile uint32_t DR2[32];
|
|
volatile uint32_t DR3[32];
|
|
volatile uint32_t DR4[32];
|
|
volatile uint32_t DR5[32];
|
|
volatile uint32_t DR6[32];
|
|
volatile uint32_t DR7[32];
|
|
volatile uint32_t DR8[32];
|
|
volatile uint32_t DR9[32];
|
|
volatile uint32_t DR10[32];
|
|
volatile uint32_t RTCCR[32];
|
|
volatile uint32_t CR[32];
|
|
volatile uint32_t CSR[32];
|
|
volatile uint32_t RESERVED_1[2][32];
|
|
volatile uint32_t DR11[32];
|
|
volatile uint32_t DR12[32];
|
|
volatile uint32_t DR13[32];
|
|
volatile uint32_t DR14[32];
|
|
volatile uint32_t DR15[32];
|
|
volatile uint32_t DR16[32];
|
|
volatile uint32_t DR17[32];
|
|
volatile uint32_t DR18[32];
|
|
volatile uint32_t DR19[32];
|
|
volatile uint32_t DR20[32];
|
|
volatile uint32_t DR21[32];
|
|
volatile uint32_t DR22[32];
|
|
volatile uint32_t DR23[32];
|
|
volatile uint32_t DR24[32];
|
|
volatile uint32_t DR25[32];
|
|
volatile uint32_t DR26[32];
|
|
volatile uint32_t DR27[32];
|
|
volatile uint32_t DR28[32];
|
|
volatile uint32_t DR29[32];
|
|
volatile uint32_t DR30[32];
|
|
volatile uint32_t DR31[32];
|
|
volatile uint32_t DR32[32];
|
|
volatile uint32_t DR33[32];
|
|
volatile uint32_t DR34[32];
|
|
volatile uint32_t DR35[32];
|
|
volatile uint32_t DR36[32];
|
|
volatile uint32_t DR37[32];
|
|
volatile uint32_t DR38[32];
|
|
volatile uint32_t DR39[32];
|
|
volatile uint32_t DR40[32];
|
|
volatile uint32_t DR41[32];
|
|
volatile uint32_t DR42[32];
|
|
} BKP_BB_Type;
|
|
|
|
typedef struct {
|
|
volatile uint32_t CR[32];
|
|
volatile uint32_t CSR[32];
|
|
} PWR_BB_Type;
|
|
|
|
typedef struct {
|
|
volatile uint32_t EVCR[32];
|
|
volatile uint32_t MAPR[32];
|
|
volatile uint32_t EXTICR1[32];
|
|
volatile uint32_t EXTICR2[32];
|
|
volatile uint32_t EXTICR3[32];
|
|
volatile uint32_t EXTICR4[32];
|
|
volatile uint32_t RESERVED_1[32];
|
|
volatile uint32_t MAPR2[32];
|
|
} AFIO_BB_Type;
|
|
|
|
typedef struct {
|
|
volatile uint32_t IMR[32];
|
|
volatile uint32_t EMR[32];
|
|
volatile uint32_t RTSR[32];
|
|
volatile uint32_t FTSR[32];
|
|
volatile uint32_t SWIER[32];
|
|
volatile uint32_t PR[32];
|
|
} EXTI_BB_Type;
|
|
|
|
typedef struct {
|
|
volatile uint32_t CRL[32];
|
|
volatile uint32_t CRH[32];
|
|
volatile uint32_t IDR[32];
|
|
volatile uint32_t ODR[32];
|
|
volatile uint32_t BSRR[32];
|
|
volatile uint32_t BRR[32];
|
|
volatile uint32_t LCKR[32];
|
|
} GPIOA_BB_Type;
|
|
|
|
typedef struct {
|
|
volatile uint32_t SR[32];
|
|
volatile uint32_t CR1[32];
|
|
volatile uint32_t CR2[32];
|
|
volatile uint32_t SMPR1[32];
|
|
volatile uint32_t SMPR2[32];
|
|
volatile uint32_t JOFR1[32];
|
|
volatile uint32_t JOFR2[32];
|
|
volatile uint32_t JOFR3[32];
|
|
volatile uint32_t JOFR4[32];
|
|
volatile uint32_t HTR[32];
|
|
volatile uint32_t LTR[32];
|
|
volatile uint32_t SQR1[32];
|
|
volatile uint32_t SQR2[32];
|
|
volatile uint32_t SQR3[32];
|
|
volatile uint32_t JSQR[32];
|
|
volatile uint32_t JDR1[32];
|
|
volatile uint32_t JDR2[32];
|
|
volatile uint32_t JDR3[32];
|
|
volatile uint32_t JDR4[32];
|
|
volatile uint32_t DR[32];
|
|
} ADC1_BB_Type;
|
|
|
|
typedef struct {
|
|
volatile uint32_t SR[32];
|
|
volatile uint32_t CR1[32];
|
|
volatile uint32_t CR2[32];
|
|
volatile uint32_t SMPR1[32];
|
|
volatile uint32_t SMPR2[32];
|
|
volatile uint32_t JOFR1[32];
|
|
volatile uint32_t JOFR2[32];
|
|
volatile uint32_t JOFR3[32];
|
|
volatile uint32_t JOFR4[32];
|
|
volatile uint32_t HTR[32];
|
|
volatile uint32_t LTR[32];
|
|
volatile uint32_t SQR1[32];
|
|
volatile uint32_t SQR2[32];
|
|
volatile uint32_t SQR3[32];
|
|
volatile uint32_t JSQR[32];
|
|
volatile uint32_t JDR1[32];
|
|
volatile uint32_t JDR2[32];
|
|
volatile uint32_t JDR3[32];
|
|
volatile uint32_t JDR4[32];
|
|
volatile uint32_t DR[32];
|
|
} ADC2_BB_Type;
|
|
|
|
typedef struct {
|
|
volatile uint32_t CR1[32];
|
|
volatile uint32_t CR2[32];
|
|
volatile uint32_t SMCR[32];
|
|
volatile uint32_t DIER[32];
|
|
volatile uint32_t SR[32];
|
|
volatile uint32_t EGR[32];
|
|
volatile uint32_t CCMR1[32];
|
|
volatile uint32_t CCMR2[32];
|
|
volatile uint32_t CCER[32];
|
|
volatile uint32_t CNT[32];
|
|
volatile uint32_t PSC[32];
|
|
volatile uint32_t ARR[32];
|
|
volatile uint32_t RCR[32];
|
|
volatile uint32_t CCR1[32];
|
|
volatile uint32_t CCR2[32];
|
|
volatile uint32_t CCR3[32];
|
|
volatile uint32_t CCR4[32];
|
|
volatile uint32_t BDTR[32];
|
|
volatile uint32_t DCR[32];
|
|
volatile uint32_t DMAR[32];
|
|
} TIM1_BB_Type;
|
|
|
|
typedef struct {
|
|
volatile uint32_t ISR[32];
|
|
volatile uint32_t IFCR[32];
|
|
volatile uint32_t CCR1[32];
|
|
volatile uint32_t CNDTR1[32];
|
|
volatile uint32_t CPAR1[32];
|
|
volatile uint32_t CMAR1[32];
|
|
volatile uint32_t RESERVED_1[32];
|
|
volatile uint32_t CCR2[32];
|
|
volatile uint32_t CNDTR2[32];
|
|
volatile uint32_t CPAR2[32];
|
|
volatile uint32_t CMAR2[32];
|
|
volatile uint32_t RESERVED_2[32];
|
|
volatile uint32_t CCR3[32];
|
|
volatile uint32_t CNDTR3[32];
|
|
volatile uint32_t CPAR3[32];
|
|
volatile uint32_t CMAR3[32];
|
|
volatile uint32_t RESERVED_3[32];
|
|
volatile uint32_t CCR4[32];
|
|
volatile uint32_t CNDTR4[32];
|
|
volatile uint32_t CPAR4[32];
|
|
volatile uint32_t CMAR4[32];
|
|
volatile uint32_t RESERVED_4[32];
|
|
volatile uint32_t CCR5[32];
|
|
volatile uint32_t CNDTR5[32];
|
|
volatile uint32_t CPAR5[32];
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volatile uint32_t CMAR5[32];
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volatile uint32_t RESERVED_5[32];
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volatile uint32_t CCR6[32];
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volatile uint32_t CNDTR6[32];
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volatile uint32_t CPAR6[32];
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volatile uint32_t CMAR6[32];
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volatile uint32_t RESERVED_6[32];
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volatile uint32_t CCR7[32];
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volatile uint32_t CNDTR7[32];
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volatile uint32_t CPAR7[32];
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volatile uint32_t CMAR7[32];
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} DMA1_BB_Type;
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typedef struct {
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volatile uint32_t CR[32];
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volatile uint32_t CFGR[32];
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volatile uint32_t CIR[32];
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volatile uint32_t APB2RSTR[32];
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volatile uint32_t APB1RSTR[32];
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volatile uint32_t AHBENR[32];
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volatile uint32_t APB2ENR[32];
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volatile uint32_t APB1ENR[32];
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volatile uint32_t BDCR[32];
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volatile uint32_t CSR[32];
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} RCC_BB_Type;
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typedef struct {
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volatile uint32_t ACR[32];
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volatile uint32_t KEYR[32];
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volatile uint32_t OPTKEYR[32];
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volatile uint32_t SR[32];
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volatile uint32_t CR[32];
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|
volatile uint32_t AR[32];
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volatile uint32_t RESERVED_1[32];
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volatile uint32_t OBR[32];
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volatile uint32_t WRPR[32];
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} FLASH_BB_Type;
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|
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typedef struct {
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volatile uint32_t DR[32];
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volatile uint32_t IDR[32];
|
|
volatile uint32_t CR[32];
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|
} CRC_BB_Type;
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|
|
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|
|
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// *****************************************************************************
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|
// * < Bit-banding base addresses > *
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|
// *****************************************************************************
|
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|
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#define TIM2_BB_BASE ((uint32_t) 0x42000000)
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#define TIM3_BB_BASE ((uint32_t) 0x42008000)
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#define TIM4_BB_BASE ((uint32_t) 0x42010000)
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#define RTC_BB_BASE ((uint32_t) 0x42050000)
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#define WWDG_BB_BASE ((uint32_t) 0x42058000)
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#define IWDG_BB_BASE ((uint32_t) 0x42060000)
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#define SPI2_BB_BASE ((uint32_t) 0x42070000)
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#define USART2_BB_BASE ((uint32_t) 0x42088000)
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#define USART3_BB_BASE ((uint32_t) 0x42090000)
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|
#define I2C1_BB_BASE ((uint32_t) 0x420A8000)
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|
#define I2C2_BB_BASE ((uint32_t) 0x420B0000)
|
|
#define USB_BB_BASE ((uint32_t) 0x420B8000)
|
|
#define CAN1_BB_BASE ((uint32_t) 0x420C8000)
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|
#define BKP_BB_BASE ((uint32_t) 0x420D8000)
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|
#define PWR_BB_BASE ((uint32_t) 0x420E0000)
|
|
#define AFIO_BB_BASE ((uint32_t) 0x42200000)
|
|
#define EXTI_BB_BASE ((uint32_t) 0x42208000)
|
|
#define GPIOA_BB_BASE ((uint32_t) 0x42210000)
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|
#define GPIOB_BB_BASE ((uint32_t) 0x42218000)
|
|
#define GPIOC_BB_BASE ((uint32_t) 0x42220000)
|
|
#define GPIOD_BB_BASE ((uint32_t) 0x42228000)
|
|
#define ADC1_BB_BASE ((uint32_t) 0x42248000)
|
|
#define ADC2_BB_BASE ((uint32_t) 0x42250000)
|
|
#define TIM1_BB_BASE ((uint32_t) 0x42258000)
|
|
#define SPI1_BB_BASE ((uint32_t) 0x42260000)
|
|
#define USART1_BB_BASE ((uint32_t) 0x42270000)
|
|
#define DMA1_BB_BASE ((uint32_t) 0x42400000)
|
|
#define RCC_BB_BASE ((uint32_t) 0x42420000)
|
|
#define FLASH_BB_BASE ((uint32_t) 0x42440000)
|
|
#define CRC_BB_BASE ((uint32_t) 0x42460000)
|
|
|
|
|
|
|
|
// *****************************************************************************
|
|
// * < Bit-banding locations assignment > *
|
|
// *****************************************************************************
|
|
|
|
#define BB_TIM2 ( (TIM2_BB_Type*) TIM2_BB_BASE )
|
|
#define BB_TIM3 ( (TIM2_BB_Type*) TIM3_BB_BASE )
|
|
#define BB_TIM4 ( (TIM2_BB_Type*) TIM4_BB_BASE )
|
|
#define BB_RTC ( (RTC_BB_Type*) RTC_BB_BASE )
|
|
#define BB_WWDG ( (WWDG_BB_Type*) WWDG_BB_BASE )
|
|
#define BB_IWDG ( (IWDG_BB_Type*) IWDG_BB_BASE )
|
|
#define BB_SPI2 ( (SPI1_BB_Type*) SPI2_BB_BASE )
|
|
#define BB_USART2 ( (USART1_BB_Type*) USART2_BB_BASE )
|
|
#define BB_USART3 ( (USART1_BB_Type*) USART3_BB_BASE )
|
|
#define BB_I2C1 ( (I2C1_BB_Type*) I2C1_BB_BASE )
|
|
#define BB_I2C2 ( (I2C1_BB_Type*) I2C2_BB_BASE )
|
|
#define BB_USB ( (USB_BB_Type*) USB_BB_BASE )
|
|
#define BB_CAN1 ( (CAN1_BB_Type*) CAN1_BB_BASE )
|
|
#define BB_BKP ( (BKP_BB_Type*) BKP_BB_BASE )
|
|
#define BB_PWR ( (PWR_BB_Type*) PWR_BB_BASE )
|
|
#define BB_AFIO ( (AFIO_BB_Type*) AFIO_BB_BASE )
|
|
#define BB_EXTI ( (EXTI_BB_Type*) EXTI_BB_BASE )
|
|
#define BB_GPIOA ( (GPIOA_BB_Type*) GPIOA_BB_BASE )
|
|
#define BB_GPIOB ( (GPIOA_BB_Type*) GPIOB_BB_BASE )
|
|
#define BB_GPIOC ( (GPIOA_BB_Type*) GPIOC_BB_BASE )
|
|
#define BB_GPIOD ( (GPIOA_BB_Type*) GPIOD_BB_BASE )
|
|
#define BB_ADC1 ( (ADC1_BB_Type*) ADC1_BB_BASE )
|
|
#define BB_ADC2 ( (ADC2_BB_Type*) ADC2_BB_BASE )
|
|
#define BB_TIM1 ( (TIM1_BB_Type*) TIM1_BB_BASE )
|
|
#define BB_SPI1 ( (SPI1_BB_Type*) SPI1_BB_BASE )
|
|
#define BB_USART1 ( (USART1_BB_Type*) USART1_BB_BASE )
|
|
#define BB_DMA1 ( (DMA1_BB_Type*) DMA1_BB_BASE )
|
|
#define BB_RCC ( (RCC_BB_Type*) RCC_BB_BASE )
|
|
#define BB_FLASH ( (FLASH_BB_Type*) FLASH_BB_BASE )
|
|
#define BB_CRC ( (CRC_BB_Type*) CRC_BB_BASE )
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|